Method of fabricating an ultra-narrow channel semiconductor device
View Patent ↗A method of forming a nanowire is disclosed. A nanowire having a first dimension is deposited on a first dielectric layer that is formed on a substrate. A sacrificial gate stack having a sacrificial dielectric layer and a sacrificial gate electrode layer is deposited over a first region of the nanowire leaving exposed a second region and a third region of the nanowire. A first spacer is deposited on each side of the sacrificial gate stack. A second dielectric layer is deposited over the first dielectric layer to cover the second region and the third region. The sacrificial gate stack is removed. The first region of the nanowire is thinned by at least one thermal oxidation process and oxide removal process to thin said first region from said first dimension to a second dimension.
1. An electronic device comprising:
a nanowire formed on a first dielectric layer formed on a substrate, said nanowire having a channel region, a first source/drain region, and a second source/drain region, said channel region being substantially smaller than each of said first source/drain region, and said second source/drain region and having no recess formed on a top surface of said nanowire;
a device gate stack formed over said channel region;
a first spacer formed on each side of said device gate stack; and
a second dielectric layer formed over said first dielectric layer, said first source/drain region, and said second source/drain region.
2. An electronic device as in claim 1 wherein said dielectric layer further comprises:
contact vias to allow to each of said first source/drain region and said second source/drain region.
3. An electronic device comprising:
a nanowire formed on a first dielectric layer formed on a substrate, said nanowire having a channel region, a first source/drain region, and a second source/drain region, said channel region being substantially smaller than each of said first source/drain region, and said second source/drain region;
a device gate stack formed over said channel region;
a first spacer formed on each side of said device gate stack; and
a second spacer formed on each side of said first spacer.
4. An electronic device comprising:
a nanowire formed on a first dielectric layer formed on a substrate, said nanowire having a channel region, a first source/drain region, and a second source/drain region, said channel region being substantially smaller than each of said first source/drain region, and said second source/drain region;
a device gate stack formed over said channel region;
a first spacer formed on each side of said device gate stack; and
a second dielectric layer formed over said first dielectric layer, said first source/drain region, and said second source/drain region; and
an epitaxial layer formed over each of said first source/drain region, and said second source/drain region to increase dimensions of said first source/drain region, and said second source/drain region.
5. An electronic device as in claim 4 further comprising:
an epitaxial layer formed over each of said first source/drain region, and said second source/drain region to increase dimensions of said first source/drain region, and said second source/drain region.
6. An electronic device as in claim 4 wherein said dielectric layer further comprises:
contact vias to allow to each of said first source/drain region and said second source/drain region.