Spacer-based patterning for tight-pitch and low-variability random access memory (RAM) bit cells and the resulting structures

1. A semiconductor structure, comprising:

a substrate having a top dielectric layer;

an array of non-volatile random access memory (RAM) bit cells disposed directly on and in contact with the top dielectric layer of the substrate, the array of non-volatile RAM bit cells comprising columns of non-volatile RAM bit cells along a first direction and rows of non-volatile RAM bit cells along a second direction orthogonal to the first direction; and

a plurality of recesses in the top dielectric layer of the substrate, along the first direction between columns of the array of non-volatile RAM bit cells.

2. The semiconductor structure of claim 1 , wherein the array of non-volatile RAM bit cells has a pitch along the first direction and has the pitch along the second direction.

3. The semiconductor structure of claim 1 , wherein each of the non-volatile RAM bit cells of the array of non-volatile RAM bit cells has, from a plan view perspective, substantially straight edges along the first direction and along the second direction and substantially rounded corners joining the straight edges.

4. The semiconductor structure of claim 1 , wherein the array of non-volatile RAM bit cells is an array of spin torque transfer random access memory (STTRAM) bit cells.

5. The semiconductor structure of claim 1 , wherein the array of non-volatile RAM bit cells is an array of resistive random access memory (RRAM) bit cells.

6. The semiconductor structure of claim 1 , wherein the array of non-volatile RAM bit cells is an array of conductive bridge random access memory (CBRAM) bit cells.

7. The semiconductor structure of claim 1 , further comprising:

an additional recess in the top dielectric layer of the substrate, between non-volatile RAM bit cells of a first pairing of adjacent rows of the array of non-volatile RAM bit cells along the second direction.

8. The semiconductor structure of claim 7 , wherein a second pairing of adjacent rows of the array of non-volatile RAM bit cells immediately adjacent the first pairing does not include an additional recess in the top dielectric layer of the substrate between non-volatile RAM bit cells of the second pairing.

9. A semiconductor structure, comprising:

a substrate having a top layer;

an array of non-volatile random access memory (RAM) bit cells disposed on the top layer of the substrate, the array of non-volatile RAM bit cells comprising columns of non-volatile RAM bit cells along a first direction and rows of non-volatile RAM bit cells along a second direction orthogonal to the first direction, wherein each of the non-volatile RAM bit cells of the array of non-volatile RAM bit cells has, from a plan view perspective, substantially straight edges along the first direction and along the second direction and substantially rounded corners joining the straight edges.

10. The semiconductor structure of claim 9 , wherein the array of non-volatile RAM bit cells has a pitch along the first direction and has the pitch along the second direction.

11. The semiconductor structure of claim 9 , further comprising:

a recess in the top layer of the substrate, between non-volatile RAM bit cells of a first pairing of adjacent rows of the array of non-volatile RAM bit cells along the second direction, wherein a second pairing of adjacent rows of the array of non-volatile RAM bit cells immediately adjacent the first pairing does not include a recess in the top layer of the substrate between non-volatile RAM bit cells of the second pairing.

12. The semiconductor structure of claim 9 , wherein the array of non-volatile RAM bit cells is an array of spin torque transfer random access memory (STTRAM) bit cells.

13. The semiconductor structure of claim 9 , wherein the array of non-volatile RAM bit cells is an array of resistive random access memory (RRAM) bit cells.

14. The semiconductor structure of claim 9 , wherein the array of non-volatile RAM bit cells is an array of conductive bridge random access memory (CBRAM) bit cells.

15. A semiconductor structure, comprising:

a substrate having a top layer;

an array of non-volatile random access memory (RAM) bit cells disposed on the top layer of the substrate, the array of non-volatile RAM bit cells comprising columns of non-volatile RAM bit cells along a first direction and rows of non-volatile RAM bit cells along a second direction orthogonal to the first direction, wherein the array of non-volatile RAM bit cells is an array of conductive bridge random access memory (CBRAM) bit cells; and

a plurality of recesses in the top layer of the substrate, along the first direction between columns of the array of non-volatile RAM bit cells.

16. The semiconductor structure of claim 15 , wherein the array of non-volatile RAM bit cells has a pitch along the first direction and has the pitch along the second direction.

17. The semiconductor structure of claim 15 , wherein each of the non-volatile RAM bit cells of the array of non-volatile RAM bit cells has, from a plan view perspective, substantially straight edges along the first direction and along the second direction and substantially rounded corners joining the straight edges.

18. The semiconductor structure of claim 15 , wherein the plurality of recesses does not extend beneath the array of non-volatile RAM bit cells.

19. The semiconductor structure of claim 18 , wherein the top layer of the substrate is a dielectric layer, and the plurality of recesses is in the dielectric layer.

20. A semiconductor structure, comprising:

a substrate having a top layer;

an array of non-volatile random access memory (RAM) bit cells disposed on the top layer of the substrate, the array of non-volatile RAM bit cells comprising columns of non-volatile RAM bit cells along a first direction and rows of non-volatile RAM bit cells along a second direction orthogonal to the first direction;

a plurality of recesses in the top layer of the substrate, along the first direction between columns of the array of non-volatile RAM bit cells; and

an additional recess in the top layer of the substrate, between non-volatile RAM bit cells of a first pairing of adjacent rows of the array of non-volatile RAM bit cells along the second direction, wherein a second pairing of adjacent rows of the array of non-volatile RAM bit cells immediately adjacent the first pairing does not include an additional recess in the top layer of the substrate between non-volatile RAM bit cells of the second pairing.

21. The semiconductor structure of claim 20 , wherein the array of non-volatile RAM bit cells has a pitch along the first direction and has the pitch along the second direction.

22. The semiconductor structure of claim 20 , wherein each of the non-volatile RAM bit cells of the array of non-volatile RAM bit cells has, from a plan view perspective, substantially straight edges along the first direction and along the second direction and substantially rounded corners joining the straight edges.

23. The semiconductor structure of claim 20 , wherein the array of non-volatile RAM bit cells is an array of spin torque transfer random access memory (STTRAM) bit cells.

24. The semiconductor structure of claim 20 , wherein the array of non-volatile RAM bit cells is an array of resistive random access memory (RRAM) bit cells.

25. The semiconductor structure of claim 20 , wherein the array of non-volatile RAM bit cells is an array of conductive bridge random access memory (CBRAM) bit cells.