Method and apparatus to process 4-operand SIMD integer multiply-accumulate instruction
View Patent ↗According to one embodiment, a processor includes an instruction decoder to receive an instruction to process a multiply-accumulate operation, the instruction having a first operand, a second operand, a third operand, and a fourth operand. The first operand is to specify a first storage location to store an accumulated value; the second operand is to specify a second storage location to store a first value and a second value; and the third operand is to specify a third storage location to store a third value. The processor further includes an execution unit coupled to the instruction decoder to perform the multiply-accumulate operation to multiply the first value with the second value to generate a multiply result and to accumulate the multiply result and at least a portion of a third value to an accumulated value based on the fourth operand.
1. A processor, comprising:
instruction decoder circuitry to decode an instruction having a field to identify a first operand, a field to identify a second operand, a field to identify a third operand, and a field to store an immediate, the identified first operand to specify a first storage location to store an accumulated value, the identified second operand to specify a second storage location to store a first value and a second value, the identified third operand to specify a third storage location to store a third value; and
execution circuitry coupled to the instruction decoder circuitry to executed the decoded instruction by multiplying the first value with the second value to generate a multiply result and accumulating the multiply result and at least a portion of the third value to the accumulated value based on the immediate fourth operand.
2. The processor of claim 1 , wherein a result of the accumulate is to be stored in the first storage location indicated by the identified first operand.
3. The processor of claim 1 , wherein the immediate is to store a value indicating the at least a portion of the third value to be added to the accumulated value.
4. The processor of claim 3 , wherein a higher portion of the third value is accumulated when the value of the fourth storage location contains a first value, and wherein a lower portion of the third value is accumulated when the value of the fourth storage location contains a second value.
5. The processor of claim 1 , wherein the identified first, second, and third operands have at least 512 bits, and wherein the execution circuitry is to perform at least four iterations of the multiply-accumulate operation, each iteration occupying at least 128 bits.
6. The processor of claim 1 , wherein a multiplication is performed between the (i+63:i) bits of the identified second operand and the (i+127:i+64) bits of the second operand, a first addition is performed between the multiplication and the (i+63:i) bits of the identified first operand, and a second addition is performed between the first addition and the (i+63:i) bits of the identified third operand as specified by the identified fourth operand.
7. The processor of claim 6 , wherein a third addition is performed between a first set of carry bits resulting from the first addition and a second set of carry bits resulting from the second addition.
8. The processor of claim 6 , wherein the second addition is performed between the first addition and the (i+127:i+64) bits of the identified third operand as specified by the immediate.
9. A method, comprising:
decoding, by an instruction decoder of a processor, an instruction having a field to identify a first operand, a field to identify a second operand, a field to identify a third operand, and an immediate, the identified first operand to specify a first storage location to store an accumulated value, the identified second operand to specify a second storage location to store a first value and a second value, the identified third operand to specify a third storage location to store a third value; and
executing the decoded instruction to multiply the first value with the second value to generate a multiply result and accumulate the multiply result and at least a portion of a third value to an accumulated value based on the immediate.
10. The method of claim 9 , further comprising: storing a result of the accumulate in the first storage location indicated by the identified first operand.
11. The method of claim 9 , wherein the immediate specifies a fourth storage location to store a value indicating the at least a portion of the third value to be added to the accumulated value.
12. The method of claim 11 , wherein a higher portion of the third value is accumulated when the value of the fourth storage location contains a first value, and wherein a lower portion of the third value is accumulated when the value of the fourth storage location contains a second value.
13. The method of claim 9 , wherein the identified first, second, and third operands have at least 512 bits.
14. The method of claim 9 , wherein for a current iteration, a multiplication is performed between the (i+63:i) bits of the identified second operand and the (i+127:i+64) bits of the identified second operand, a first addition is performed between the multiplication and the (i+63:i) bits of the identified first operand, and a second addition is performed between the first addition and the (i+63:i) bits of the identified third operand as specified by the immediate.
15. The method of claim 14 , wherein a third addition is performed between a first set of carry bits resulting from the first addition and a second set of carry bits resulting from the second addition.
16. The method of claim 14 , wherein the second addition is performed between the first addition and the (i+127:i+64) bits of the identified third operand as specified by the immediate.
17. A data processing system, comprising:
an interconnect;
a processor coupled to the interconnect to decode an instruction having field to identify a first operand, a field to identify a second operand, a field to identify a third operand, and a field to store an immediate, the identified first operand to specify a first storage location to store an accumulated value, the identified second operand to specify a second storage location to store a first value and a second value, the identified third operand to specify a third storage location to store a third value, and the processor to execute the decoded instruction to multiply the first value with the second value to generate a multiply result and accumulate the multiply result and at least a portion of a third value to the accumulated value based on the immediate; and
a dynamic random access (DRAM) coupled to the interconnect.
18. The system of claim 17 , wherein a result of the accumulation is to be stored in the first storage location indicated by the identified first operand.
19. The system of claim 17 , wherein the immediate is to specify a fourth storage location to store a value indicating the at least a portion of the third value to be added to the accumulated value.
20. The system of claim 19 , wherein a higher portion of the third value is accumulated when the value of the fourth storage location contains a first value, and wherein a lower portion of the third value is accumulated when the value of the fourth storage location contains a second value.
21. The system of claim 17 , wherein the identified first, second, and third operands have at least 512 bits, and wherein the execution circuitry is to perform at least four iterations of the multiply-accumulate operation, each iteration occupying at least 128 bits.
22. The system of claim 17 , wherein for a current iteration, a multiplication is performed between the (i+63:i) bits of the identified second operand and the (i+127:i+64) bits of the identified second operand, a first addition is performed between the multiplication and the (i+63:i) bits of the identified first operand, and a second addition is performed between the first addition and the (i+63:i) bits of the identified third operand as specified by the immediate.
23. The system of claim 22 , wherein a third addition is performed between a first set of carry bits resulting from the first addition and a second set of carry bits resulting from the second addition.
24. The system of claim 22 , wherein the second addition is performed between the first addition and the (i+127:i+64) bits of the identified third operand as specified by the immediate.