In-lane vector shuffle instructions
In-lane vector shuffle operations are described. In one embodiment a shuffle instruction specifies a field of per-lane control bits, a source operand and a destination operand, these operands having corresponding lanes, each lane divided into corresponding portions of multiple data elements. Sets of data elements are selected from corresponding portions of every lane of the source operand according to per-lane control bits. Elements of these sets are copied to specified fields in corresponding portions of every lane of the destination operand. Another embodiment of the shuffle instruction also specifies a second source operand, all operands having corresponding lanes divided into multiple data elements. A set selected according to per-lane control bits contains data elements from every lane portion of a first source operand and data elements from every corresponding lane portion of the second source operand. Set elements are copied to specified fields in every lane of the destination operand.
1. A processor comprising:
a decode unit including circuitry to decode a single instruction specifying a first source operand, a second source operand, a destination operand, and an immediate operand, wherein the first source operand, the second source operand, and the destination operand each have a first lane and a second lane, wherein the first lane of the first source operand is to store data elements X 4 , X 3 , X 2 , and X 1 (X 4 -X 1 ), wherein the second lane of the first source operand is to store data elements X 8 , X 7 , X 6 , and X 5 (X 8 -X 5 ), wherein the first lane of the second source operand is to store data elements Y 4 , Y 3 , Y 2 , and Y 1 (Y 4 -Y 1 ), wherein the second lane of the second source operand is to store data elements Y 8 , Y 7 , Y 6 , and Y 5 (Y 8 -Y 5 ), and wherein the immediate operand is to specify a first plurality of control bits, a second plurality of control bits, a third plurality of control bits, and a fourth plurality of control bits; and
an execution unit coupled with the decode unit, the execution unit to perform the single instruction, the execution unit including circuitry to use the first, second, third, and fourth pluralities of control bits for each of the first and second lanes of the destination operand, the execution unit to:
copy one of the data elements X 4 -X 1 specified by the first plurality of control bits to a first data element position of the first lane of the destination operand, copy one of the data elements X 4 -X 1 specified by the second plurality of control bits to a second data element position of the first lane of the destination operand, copy one of the data elements Y 4 -Y 1 specified by the third plurality of control bits to a third data element position of the first lane of the destination operand, and copy one of the data elements Y 4 -Y 1 specified by the fourth plurality of control bits to a fourth data element position of the first lane of the destination operand; and
copy one of the data elements X 8 -X 5 specified by the first plurality of control bits to a first data element position of the second lane of the destination operand, copy one of the data elements X 8 -X 5 specified by the second plurality of control bits to a second data element position of the second lane of the destination operand, copy one of the data elements Y 8 -Y 5 specified by the third plurality of control bits to a third data element position of the second lane of the destination operand, and copy one of the data elements Y 8 -Y 5 specified by the fourth plurality of control bits to a fourth data element position of the second lane of the destination operand.
2. The processor of claim 1 , wherein the first source operand is a 256-bit operand, and wherein each of the first lane of the first source operand and the second lane of the first source operand is a 128-bit lane.
3. The processor of claim 2 , wherein each of the data elements X 4 -X 1 is a 32-bit data element and each of the data elements X 8 -X 5 is a 32-bit data element.
4. The processor of claim 1 , wherein the second source operand is a 256-bit operand, and wherein each of the first lane of the second source operand and the second lane of the second source operand is a 128-bit lane.
5. The processor of claim 4 , wherein each of the data elements Y 4 -Y 1 is a 32-bit data element and each of the data elements Y 8 -Y 5 is a 32-bit data element.
6. The processor of claim 1 , wherein the immediate operand is an 8-bit operand.
7. The processor of claim 6 , wherein each of the first plurality of control bits, the second plurality of control bits, the third plurality of control bits, and the fourth plurality of control bits consists of 2 bits.
8. The processor of claim 1 , wherein the destination operand is a 256-bit operand, and wherein each of the first lane of the destination operand and the second lane of the destination operand is a 128-bit lane.
9. The processor of claim 1 , wherein the first lane of the first source operand occupies one half of the first source operand and the second lane of the first source operand occupies another half of the first source operand.
10. A system comprising:
a plurality of processors;
a memory; and
a bus to communicatively couple a given processor of the plurality of processors to a plurality of other system components, wherein the given processor includes:
a decode unit including circuitry to decode a single instruction specifying a first source operand, a second source operand, a destination operand, and an immediate operand, wherein the first source operand, the second source operand, and the destination operand each have a first lane and a second lane, wherein the first lane of the first source operand is to store data elements X 4 , X 3 , X 2 , and X 1 (X 4 -X 1 ), wherein the second lane of the first source operand is to store data elements X 8 , X 7 , X 6 , and X 5 (X 8 -X 5 ), wherein the first lane of the second source operand is to store data elements Y 4 , Y 3 , Y 2 , and Y 1 (Y 4 -Y 1 ), wherein the second lane of the second source operand is to store data elements Y 8 , Y 7 , Y 6 , and Y 5 (Y 8 -Y 5 ), and wherein the immediate operand is to specify a first plurality of control bits, a second plurality of control bits, a third plurality of control bits, and a fourth plurality of control bits; and
an execution unit coupled with the decode unit, the execution unit including circuitry to use the first, second, third, and fourth pluralities of control bits for each of the first and second lanes of the destination operand, the execution unit to:
copy one of the data elements X 4 -X 1 specified by the first plurality of control bits to a first data element position of the first lane of the destination operand, copy one of the data elements X 4 -X 1 specified by the second plurality of control bits to a second data element position of the first lane of the destination operand, copy one of the data elements Y 4 -Y 1 specified by the third plurality of control bits to a third data element position of the first lane of the destination operand, and copy one of the data elements Y 4 -Y 1 specified by the fourth plurality of control bits to a fourth data element position of the first lane of the destination operand; and
copy one of the data elements X 8 -X 5 specified by the first plurality of control bits to a first data element position of the second lane of the destination operand, copy one of the data elements X 8 -X 5 specified by the second plurality of control bits to a second data element position of the second lane of the destination operand, copy one of the data elements Y 8 -Y 5 specified by the third plurality of control bits to a third data element position of the second lane of the destination operand, and copy one of the data elements Y 8 -Y 5 specified by the fourth plurality of control bits to a fourth data element position of the second lane of the destination operand.
11. The system of claim 10 , wherein the first source operand is a 256-bit operand, and wherein each of the first lane of the first source operand and the second lane of the first source operand is a 128-bit lane.
12. The system of claim 11 , wherein each of the data elements X 4 -X 1 is a 32-bit data element and each of the data elements X 8 -X 5 is a 32-bit data element.
13. The system of claim 10 , wherein the second source operand is a 256-bit operand, and wherein each of the first lane of the second source operand and the second lane of the second source operand is a 128-bit lane.
14. The system of claim 13 , wherein each of the data elements Y 4 -Y 1 is a 32-bit data element and each of the data elements Y 8 -Y 5 is a 32-bit data element.
15. The system of claim 10 , wherein the immediate operand is an 8-bit operand.
16. The system of claim 15 , wherein each of the first plurality of control bits, the second plurality of control bits, the third plurality of control bits, and the fourth plurality of control bits consists of 2 bits.
17. The system of claim 10 , wherein the destination operand is a 256-bit operand, and wherein each of the first lane of the destination operand and the second lane of the destination operand is a 128-bit lane.
18. The system of claim 10 , wherein the first lane of the first source operand occupies one half of the first source operand and the second lane of the first source operand occupies another half of the first source operand.
19. A system comprising:
a memory; and
a processor coupled with the memory, wherein the processor includes:
a decode unit including circuitry to decode a single instruction specifying a first source operand, a second source operand, a destination operand, and an immediate operand, wherein the first source operand, the second source operand, and the destination operand each have a first lane and a second lane, wherein the first lane of the first source operand is to store data elements X 4 , X 3 , X 2 , and X 1 (X 4 -X 1 ), wherein the second lane of the first source operand is to store data elements X 8 , X 7 , X 6 , and X 5 (X 8 -X 5 ), wherein the first lane of the second source operand is to store data elements Y 4 , Y 3 , Y 2 , and Y 1 (Y 4 -Y 1 ), wherein the second lane of the second source operand is to store data elements Y 8 , Y 7 , Y 6 , and Y 5 (Y 8 -Y 5 ), and wherein the immediate operand is to specify a first plurality of control bits, a second plurality of control bits, a third plurality of control bits, and a fourth plurality of control bits; and
an execution unit coupled with the decode unit, the execution unit including circuitry to use the first, second, third, and fourth pluralities of control bits for each of the first and second lanes of the destination operand, the execution unit to:
copy one of the data elements X 4 -X 1 specified by the first plurality of control bits to a first data element position of the first lane of the destination operand, copy one of the data elements X 4 -X 1 specified by the second plurality of control bits to a second data element position of the first lane of the destination operand, copy one of the data elements Y 4 -Y 1 specified by the third plurality of control bits to a third data element position of the first lane of the destination operand, and copy one of the data elements Y 4 -Y 1 specified by the fourth plurality of control bits to a fourth data element position of the first lane of the destination operand; and
copy one of the data elements X 8 -X 5 specified by the first plurality of control bits to a first data element position of the second lane of the destination operand, copy one of the data elements X 8 -X 5 specified by the second plurality of control bits to a second data element position of the second lane of the destination operand, copy one of the data elements Y 8 -Y 5 specified by the third plurality of control bits to a third data element position of the second lane of the destination operand, and copy one of the data elements Y 8 -Y 5 specified by the fourth plurality of control bits to a fourth data element position of the second lane of the destination operand.
20. The system of claim 19 , wherein the first source operand is a 256-bit operand, and wherein each of the first lane of the first source operand and the second lane of the first source operand is a 128-bit lane.
21. The system of claim 20 , wherein each of the data elements X 4 -X 1 is a 32-bit data element and each of the data elements X 8 -X 5 is a 32-bit data element.
22. The system of claim 19 , wherein the second source operand is a 256-bit operand, and wherein each of the first lane of the second source operand and the second lane of the second source operand is a 128-bit lane.
23. The system of claim 22 , wherein each of the data elements Y 4 -Y 1 is a 32-bit data element and each of the data elements Y 8 -Y 5 is a 32-bit data element.
24. The system of claim 19 , wherein the immediate operand is an 8-bit operand.
25. The system of claim 24 , wherein each of the first plurality of control bits, the second plurality of control bits, the third plurality of control bits, and the fourth plurality of control bits consists of 2 bits.
26. The system of claim 19 , wherein the destination operand is a 256-bit operand, and wherein each of the first lane of the destination operand and the second lane of the destination operand is a 128-bit lane.
27. The system of claim 19 , wherein the first lane of the first source operand occupies one half of the first source operand and the second lane of the first source operand occupies another half of the first source operand.