IP Library Granted Patent US 9,859,278
Granted Patent B2
US 9,859,278 · App. 15/037,618 · Granted Jan 2, 2018

Bi-axial tensile strained GE channel for CMOS

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Quick Facts
Patent No.
US 9,859,278
App. No.
15/037,618
Granted
Jan 2, 2018
Kind
B2
Abstract

An apparatus including a complimentary metal oxide semiconductor (CMOS) inverter including an n-channel metal oxide semiconductor field effect transistor (MOSFET); and a p-channel MOSFET, wherein a material of a channel in the n-channel MOSFET and a material of a channel in the p-channel MOSFET is subject to a bi-axial tensile strain. A method including forming an n-channel metal oxide semiconductor field effect transistor (MOSFET); forming a p-channel MOSFET; and connecting the gate electrodes and the drain regions of the n-channel MOSFET and the p-channel MOSFET, wherein a material of the channel in the n-channel MOSFET and a material of the channel in the p-channel MOSFET is subject to a bi-axial tensile strain.

Claims (27)

1. An apparatus comprising:

a complimentary metal oxide semiconductor (CMOS) inverter comprising an n-channel metal oxide semiconductor field effect transistor (MOSFET) and a p-channel MOSFET,

wherein a material of a channel in the n-channel MOSFET and a material of a channel in the p-channel MOSFET is each subject to a bi-axial tensile strain, and

wherein the channel of each of the n-channel MOSFET and the p-channel MOSFET are disposed on a buffer layer and the buffer layer comprises a material having a larger lattice constant than a lattice constant of a material of the channel in the n-channel MOSFET and a material of the channel in the p-channel MOSFET.

2. The apparatus of claim 1 , wherein the material of the channel in the n-channel MOSFET and the material of the channel in the p-channel MOSFET are the same.

3. The apparatus of claim 1 , wherein the material of the channel in the n-channel MOSFET and the material of the channel in the p-channel MOSFET are each germanium.

4. The apparatus of claim 1 , wherein a material for the buffer layer comprises a Group III-V compound semiconductor material.

5. The apparatus of claim 1 , wherein the n-channel MOSFET and the p-channel MOSFET are planar transistors.

6. The apparatus of claim 1 , wherein the material of the channel in the n-channel MOSFET and the material of the channel in the p-channel MOSFET each has a lattice constant that is less than a lattice constant of a material for a respective gate electrode.

7. The apparatus of claim 6 , wherein the respective gate electrode has a length greater than 100 nanometers.

8. An apparatus comprising:

an n-channel metal oxide semiconductor field effect transistor (MOSFET) comprising a gate electrode, a source region, a drain region and a channel; and

a p-channel MOSFET comprising a gate electrode, a source region, a drain region and a channel,

wherein the gate electrode of the n-channel MOSFET is coupled to the gate electrode of the p-channel MOSFET and the drain of the n-channel MOSFET is coupled to the drain of the p-channel MOSFET,

wherein a material of the channel in the n-channel MOSFET and a material of the channel in the p-channel MOSFET is common and subject to a bi-axial tensile strain, and

wherein the channel of each of the n-channel MOSFET and the p-channel MOSFET is disposed on a buffer layer and the buffer layer comprises a material having a larger lattice constant than a lattice constant of the material of the channel in the n-channel MOSFET and a material of the channel in the p-channel MOSFET.

9. The apparatus of claim 8 , wherein a material for the buffer layer comprises a Group III-V compound semiconductor material.

10. The apparatus of claim 8 , wherein the n-channel MOSFET and the p-channel MOSFET are planar transistors.

11. The apparatus of claim 8 , wherein the common material of the channel in the n-channel MOSFET and a material of the channel in the p-channel MOSFET has a lattice constant that is less than a lattice constant of a material for the respective gate electrode.

12. The apparatus of claim 11 , wherein the gate electrode has a length greater than 100 nanometers.

13. The apparatus of claim 11 , wherein each of the channel of the n-channel MOSFET and the channel of the p-channel MOSFET comprises a nanoribbon.

14. An apparatus comprising:

an n-channel metal oxide semiconductor field effect transistor (MOSFET) comprising a gate electrode, a source region, a drain region and a channel; and

a p-channel MOSFET comprising a gate electrode, a source region, a drain region and a channel,

wherein the gate electrode of the n-channel MOSFET is coupled to the gate electrode of the p-channel MOSFET and the drain of the n-channel MOSFET is coupled to the drain of the p-channel MOSFET,

wherein a material of the channel in the n-channel MOSFET and a material of the channel in the p-channel MOSFET is subject to a bi-axial tensile strain, and

wherein the material of the channel in the n-channel MOSFET and the material of the channel in the p-channel MOSFET that is common is germanium.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2022
From: INTEL CORPORATION
To: TAHOE RESEARCH, LTD.
Reel/Frame 061175/0176 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 18, 2016
From: MAJHI, PRASHANT; MUKHERJEE, NILOY; PILLARISETTY, RAVI; RACHMADY, WILLY; CHAU, ROBERT S.
To: INTEL CORPORATION
Reel/Frame 038638/0443 →