Gate-induced strain for MOS performance improvement

1. A method comprising:

forming a device on a substrate, the device including a gate electrode on a surface of the substrate and a first junction region and a second junction region in the substrate adjacent the gate electrode;

forming tip implants adjacent to the first junction region and the second junction region, wherein the tip implants (i) are formed within the substrate, (ii) are situated beneath the gate electrode, and (iii) extend past a sidewall of the gate electrode;

forming a straining layer on the gate electrode, the straining layer patterned to correspond with a dimension of the gate electrode; and

controlling a thickness of the straining layer relative to a thickness of the gate electrode such that a strain placed on a lattice of the gate electrode is less than ten percent.

2. The method of claim 1 , wherein forming the straining layer comprises forming the straining layer of a different lattice spacing than a lattice spacing of the gate electrode to cause a strain in the substrate.

3. The method of claim 1 , wherein forming the straining layer comprises a chemical vapor deposition sufficient to form an epitaxial layer of a straining material.

4. The method of claim 1 , wherein the straining layer comprises silicon doped with an element comprising a covalent radius larger than silicon.

5. The method of claim 1 , wherein forming a straining layer comprises doping a portion of a material of the gate electrode.

6. The method of claim 1 , wherein the straining layer comprises a material having a coefficient of linear thermal expansion that is different than a coefficient of linear thermal expansion of a material of the gate electrode.