Metal gate transistors with epitaxial source and drain regions

1. A semiconductor process comprising:

growing an un-doped or lightly doped silicon layer on a heavily doped substrate;

forming an insulating layer on the silicon layer;

forming sacrificial polysilicon gates on the insulating layer;

etching the silicon layer and undercutting the gates so as to form silicon channel regions under the polysilicon gates;

growing source and drain regions from the substrate which extend into the undercutting adjacent to the silicon channel regions;

removing the polysilicon gates; and

forming metal gates in place of the polysilicon gates.

2. The process of claim 1 , wherein the processing steps of claim 1 are carried out at low enough temperatures to prevent dopant from the substrate to substantially dope the silicon layer or silicon channel regions formed from the silicon layer.

3. The process of claim 1 , wherein the etching of the silicon layer is done with a wet etchant which etches the silicon layer at a faster rate than the silicon substrate.

4. The process of claim 2 , wherein the source and drain regions are selectively grown regions of silicon or silicon-germanium.

5. The process of claim 4 , wherein the source and drain regions are heavily doped regions.

6. The process of claim 1 , wherein:

the source and drain regions comprise first and second source and drain regions;

the first source and drain regions are selectively grown and heavily doped with an n-type dopant, and

the second source and drain regions are selectively grown and heavily doped with a p-type dopant.

7. The process of claim 6 , wherein:

the metal gates comprise first metal gates and second metal gates;

the first metal gates are formed above the first source and drain regions and have a work function of between 4.0 to 4.6 eV; and

the second metal gates are formed above the second source and drain regions and have a work function of between 4.6 to 5.2 eV.

8. The process of claim 6 , wherein the forming of the metal gates comprises:

removing the polysilicon gates disposed above the first source and drain regions;

depositing a first metal;

polishing away the first metal above the second source and drain regions;

removing the polysilicon gates disposed above the second source and drain regions; and

depositing a second metal.

9. The process of claim 8 , wherein the first metal has a work function of between 4.0 to 4.6 eV, and the second metal has a work function of between 4.6 and 5.2 eV.

10. A process for forming complementary transistors comprising:

forming a lightly doped or un-doped monocrystalline layer on a heavily doped monocrystalline substrate;

forming temporary polysilicon gates insulated from the monocrystalline layer;

etching the monocrystalline layer to form channel regions for the transistors, undercutting the polysilicon gates;

growing a first plurality of monocrystalline source and drain regions doped with an n-type dopant, extending from opposite sides of a first plurality of the channel regions including within the undercutting of the polysilicon gates disposed above the first plurality of source and drain regions;

growing a second plurality of monocrystalline source and drain regions doped with a p-type dopant, extending from opposite sides of a second plurality of the channel regions including within the undercutting of the polysilicon gates disposed above the second plurality of source and drain regions;

replacing the polysilicon gates associated with the first plurality of source and drain regions with a first metal; and

replacing the polysilicon gates associated with the second plurality of source and drain regions with a second metal.

11. The process of claim 10 , wherein first side spacers are formed on the polysilicon gates before the etching of the layer.

12. The process of claim 11 , wherein second side spacers are formed on the first spacers following the formation of the first and second source and drain regions.

13. The process of claim 12 , including further doping the first and second source and drain regions and the substrate in alignment with the second spacers.

14. The process of claim 10 , wherein the first metal has a work function of between 4.0 to 4.6 eV, and the second metal has a work function of between 4.6 to 5.2 eV.