Embedded power gating
View Patent ↗With embodiments disclosed herein, the distribution of gated power is done using on-die layers without having to come back out and use package layers.
1. An IC device, comprising:
a package substrate having an ungated supply grid; and
an IC die having: (i) circuitry to receive one or more gated supplies, and (ii) a plurality of embedded power gate (EPG) transistors coupled between the ungated power grid and said circuitry to controllably provide the one or more gated supplies to the circuitry, the IC die having a plurality of die layers, the one or more gated supplies being distributed to said circuitry through the plurality of die layers, wherein the circuitry is divided into separate gated supply domains each having an associated gated supply from the one or more gated supplies, and wherein the circuitry corresponds to a core of a processor.
2. The device of claim 1 , in which no gated supply is conveyed through the package substrate.
3. The device of claim 1 , in which the die layers comprise at least six layers to implement a gated supply grid to provide the one or more gated supplies.
4. The device of claim 1 , in which the ungated grid is coupled to the EPG transistors by way of C4 solder bumps.
5. The device of claim 1 , in which the EPG transistors are disposed in evenly spaced strips.
6. The device of claim 1 , in which the die layers comprise layers proximal and distal to the circuitry.
7. The device of claim 6 , in which an EPG transistor is coupled to circuitry elements that are close to it through proximal die layers and to circuitry elements that are farther away through the distal layers.
8. A system, comprising:
(a) a microprocessor including: a package substrate having an ungated supply grid, and
an IC die having:
(i) core logic circuitry to receive one or more gated supplies, and
(ii) a plurality of embedded power gate (EPG) transistors coupled between the ungated power grid and said core logic circuitry to controllably provide the one or more gated supplies to the core logic circuitry, the IC die having a plurality of die layers, the one or more gated supplies being distributed to said core logic circuitry through the plurality of die layers
(b) an antenna; and
(c) a wireless interface coupled to the microprocessor and to the antenna to communicatively link the microprocessor to a wireless network.
9. The system of claim 8 , in which the circuitry is divided into separate gated supply domains each having an associated gated supply from the one or more gated supplies.
10. The system of claim 8 , in which no gated supply is conveyed through the package substrate.
11. The system of claim 8 , in which the die layers comprise at least six layers to implement a gated supply grid to provide the one or more gated supplies.
12. The system of claim 8 , in which the circuitry corresponds to a core of a processor.