High density interconnect device and method
Embodiments that allow both high density and low density interconnection between microelectronic die and motherboard via Direct Chip Attach (DCA) are described. In some embodiments, microelectronic die have a high density interconnect with a small bump pitch located along one edge and a lower density connection region with a larger bump pitch located in other regions of the die. The high density interconnect regions between die are interconnected using an interconnecting bridge made out of a material that can support high density interconnect manufactured into it, such as silicon. The lower density connection regions are used to attach interconnected die directly to a board using DCA. The high density interconnect can utilize current Controlled Collapsed Chip Connection (C4) spacing when interconnecting die with an interconnecting bridge, while allowing much larger spacing on circuit boards.
1. A system comprising;
a first die having a first die edge and first die surface, the first die comprising:
a first die high density interconnect located adjacent to the first die edge on the first die surface, the first die high density interconnect having a first bump pitch; and
a first die connection region located on the first die surface, the first die connection region having a second bump pitch; and
a second die having a second die edge and a second die surface, the second die comprising:
a second die high density interconnect located adjacent to the second die edge on the second die surface, the second die high density interconnect having the first hump pitch; and
a second die connection region located on the second die surface, the second die connection region having a third bump pitch; and
a bridge having a plurality of high density interconnects having the first bump pitch, one of the plurality of high density interconnects connected to the first die high density interconnect and another of the plurality of high density interconnects connected to the second die high density interconnect; and
wherein the second bump pitch is a direct chip attach (DCA) pitch sized to attach to a circuit board.
2. The system of claim 1 , die connection region comprises input/output connections.
3. The system of claim 2 , wherein the first die connection is located on the first die surface adjacent to a second edge of the first die.
4. The system of claim 3 , wherein the first die further comprises a power connection region located centrally on the first die surface.
5. The system of claim 1 , wherein the second die connection region comprises power connections.
6. The system of claim 1 , wherein the first bump pitch is smaller than the second bump pitch, and the first bump pitch is smaller than the third bump pitch.
7. The system of claim 1 , wherein the second bump pitch is about equal to the third bump pitch.
8. The system of claim 1 , wherein the first die is a System On Chip (SOC) die, and the second die is a memory die.