High-voltage transistor architectures, processes of forming same, and systems containing same
View Patent ↗An apparatus includes a first device with a metal gate and a drain well that experiences a series resistance that drops a drain contact voltage from 10 V to 4-6 V at a junction between the drain well and a channel under the gate. The apparatus includes an interlayer dielectric layer (ILD 0 ) disposed above and on the drain well and a salicide drain contact in the drain well. The apparatus also includes a subsequent device that is located in a region different from the first device that operates at a voltage lower than the first device.
1. A system comprising:
a first device, in a first region of a semiconductive substrate, which comprises:
a channel in the semiconductive substrate;
a gate electrode on the channel;
a source implant on a first side of the gate electrode and a drain implant on a second side of the gate electrode;
a drain well in the semiconductive substrate that forms a junction with the channel;
a salicide source contact pad on the semiconductive substrate;
a salicide drain contact pad on the drain well, wherein the salicide drain contact pad is located farther from the second side than the source contact pad is located from the first side; and
an interlayer dielectric layer (ILD0) on the salicide drain contact pad and the drain well;
a second device in a second region of the semiconductive substrate; and
a third device in a third region of the semiconductive substrate;
wherein the first device is configured to operate at a voltage higher than the second device;
wherein the third device is configured to operate at a voltage lower than the second device.
2. The system of claim 1 , wherein resistance between the drain implant and the channel is greater than resistance between the source implant and the channel.
3. The system of claim 1 , wherein resistivity between the drain implant and the channel is greater than resistivity between the source implant and the channel.
4. The system of claim 1 , wherein (a) the gate electrode is a high-K metal gate electrode, (b) the first device includes an oxide dielectric on the channel, and (c) a high-K dielectric is between the oxide dielectric and the gate electrode.
5. The system of claim 1 , further including a source contact that penetrates the ILD0 and wherein the source contact is symmetrical to the source contact pad.
6. The system of claim 1 , further including:
a source contact that penetrates the ILD0 and contacts the salicide source contact pad; and
a drain contact that penetrates the ILD0 and contacts the salicide drain contact pad;
wherein the ILD0 is on the salicide source contact pad.
7. The system of claim 1 , wherein the gate electrode is part of a gate, further including:
a source contact that penetrates the ILD0 and contacts the salicide source contact pad; and
a drain contact that penetrates the ILD0 and contacts the salicide drain contact pad;
wherein the ILD0 is on the gate.
8. The system of claim 1 , wherein the gate electrode is part of a gate, further including:
a source contact that penetrates the ILD0 and contacts the salicide source contact pad; and
a drain contact that penetrates the ILD0 and contacts the salicide drain contact pad;
wherein the ILD0 is on the salicide source contact pad and on the gate.
9. A system comprising:
a first device, in a first region of a semiconductive substrate, which comprises:
a channel in a semiconductive substrate;
a gate electrode on the channel;
a source implant on a first side of the gate electrode and a drain implant on a second side of the gate electrode;
a drain well in the semiconductive substrate that forms a junction with the channel;
a salicide source contact pad in the semiconductive substrate;
a salicide drain contact pad in the drain well, wherein the salicide drain contact pad is located farther from the second side than the source contact pad is located from the first side; and
an interlayer dielectric layer (ILD0);
a second device in a second region of the semiconductive substrate; and
a third device in a third region of the semiconductive substrate;
wherein the first device is configured to operate at a voltage higher than the second device;
wherein the third device is configured to operate at a voltage lower than the second device.
10. The system of claim 9 , wherein resistance between the drain implant and the channel is greater than resistance between the source implant and the channel.
11. The system of claim 9 , wherein resistivity between the drain implant and the channel is greater than resistivity between the source implant and the channel.
12. The system of claim 9 , wherein (a) the gate electrode is a high-K metal gate electrode, (b) the first device includes an oxide dielectric on the channel, and (c) a high-K dielectric is between the oxide dielectric and the gate electrode.
13. The system of claim 9 , further including a source contact that penetrates the ILD0 and wherein the source contact is symmetrical to the source contact pad.
14. The system of claim 9 , further including:
a source contact that penetrates the ILD0 and contacts the salicide source contact pad; and
a drain contact that penetrates the ILD0 and contacts the salicide drain contact pad;
wherein the ILD0 is on the salicide source contact pad, the salicide drain contact pad, and the drain well.
15. The system of claim 9 , wherein the gate electrode is part of a gate, further including:
a source contact that penetrates the ILD0 and contacts the salicide source contact pad; and
a drain contact that penetrates the ILD0 and contacts the salicide drain contact pad;
wherein the ILD0 is on the gate.
16. The system of claim 9 , wherein the gate electrode is part of a gate, further including:
a source contact that penetrates the ILD0 and contacts the salicide source contact pad; and
a drain contact that penetrates the ILD0 and contacts the salicide drain contact pad;
wherein the ILD0 is on the salicide source contact pad and on the gate.