Strain inducing semiconductor regions
View Patent ↗A method to form a strain-inducing semiconductor region is described. In one embodiment, formation of a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In another embodiment, a semiconductor region with a crystalline lattice of one or more species of charge-neutral lattice-forming atoms imparts a strain to a crystalline substrate, wherein the lattice constant of the semiconductor region is different from that of the crystalline substrate, and wherein all species of charge-neutral lattice-forming atoms of the semiconductor region are contained in the crystalline substrate.
1. A semiconductor device, comprising:
a crystalline substrate; and
a transistor disposed above the substrate, the transistor comprising:
a channel region comprising a Si x Ge 1-x material, the channel region having a top surface and a pair of laterally opposing sidewalls;
a gate dielectric layer formed on the top surface of the channel region and adjacent the pair of sidewalls of the channel region;
a gate electrode formed on the gate dielectric layer;
a pair of gate isolation spacers formed adjacent to the gate electrode;
an epitaxially-grown source region disposed laterally and directly adjacent to a first end of the channel region, the source region having a top surface and a pair of laterally opposing sidewall surfaces; and
an epitaxially-grown drain region disposed laterally and directly adjacent to a second end of the channel region, the drain region having a top surface and a pair of laterally opposing sidewall surfaces,
wherein the source and drain regions comprise a Si y Ge 1-y material directly adjacent to the channel region comprising the Si x Ge 1-x material, 0<x<1, and y<x.
2. The semiconductor device of claim 1 , wherein the substrate further comprises germanium.
3. The semiconductor device of claim 1 , wherein the channel region comprises a Si 0.5 Ge 0.5 material.
4. The semiconductor device of claim 3 , wherein the source and drain regions comprise a Si y Ge 1-y material and 0<y<0.5.
5. The semiconductor device of claim 1 , wherein the epitaxially-grown source region and the epitaxially-grown drain region together impart a uniaxial strain to the channel region.
6. The semiconductor device of claim 5 , wherein the uniaxial strain is a uniaxial compressive strain.
7. The semiconductor device of claim 1 , wherein the semiconductor device is a P-type MOS-FET.
8. The semiconductor device of claim 1 , wherein the epitaxially-grown source region and the epitaxially-grown drain region have a lattice constant that is greater than a lattice constant of the channel region by a factor of at least 0.1%.
9. The semiconductor device of claim 1 , wherein gate electrode is a metal gate electrode, and wherein the gate dielectric layer is a high-K gate dielectric layer.