Adaptive digital phase locked loop
View Patent ↗In some embodiments, a digital PLL (DPLL) is disclosed with a dynamically controllable filter for changing the effective DPLL bandwidth in response to one or more real-time performance parameters such as phase error.
1. A chip having a digital phase locked loop (DPLL), the chip comprising:
a filter for varying loop bandwidth of the DPLL when the DPLL is in operation, wherein the DPLL implements at least one of reference clock dithering or sigma-delta modulation; and
a control unit to adjust the loop bandwidth through control of the filter according to a phase error, wherein the control unit to adjust the loop bandwidth at speeds up to a sampling frequency for the filter.
2. The chip of claim 1 , wherein the control unit having a phase interpreter to identify phase error.
3. The chip of claim 1 , wherein the filter has a dominant pole that is greater than a dominant zero in the filter.
4. The chip of claim 1 , wherein the control unit to adjust the loop bandwidth by increasing loop bandwidth when the phase error increases.
5. The chip of claim 1 , wherein the control unit to adjust the loop bandwidth by reducing loop bandwidth when the phase error reduces.
6. The chip of claim 1 , wherein the filter is a digital filter.
7. The chip of claim 1 , wherein the DPLL comprises:
a digital phase-frequency detector;
a digitally controlled oscillator; and
a divider.
8. The chip of claim 7 , wherein the control unit to identify the phase error from the digital phase-frequency detector.
9. The chip of claim 1 , wherein the phase interpreter to calculate the phase error by scaling a raw phase error value derived from the filter.
10. The chip of claim 1 , wherein the filter comprises at least one of:
an integrator;
a multiplier; or
a summer.
11. The chip of claim 1 , wherein the DPLL is an all digital DPLL.
12. The chip of claim 1 , wherein the filter is characterized by two or more coefficients.
13. The chip of claim 1 , wherein the control unit to monitor a scale and to adjust the loop bandwidth through control of the filter in response to one or more performance parameters of the DPLL being above or below the monitored scale.
14. The chip of claim 13 , wherein the one or more performance parameters of the DPLL includes at least one of: phase error or frequency error.
15. A chip having a digital phase locked loop (DPLL), the chip comprising:
a filter for varying loop bandwidth of the DPLL when the DPLL is in operation, wherein the DPLL implements at least one of reference clock dithering or sigma-delta modulation; and
a control unit to adjust the loop bandwidth through control of the filter in response to one or more performance parameters of the DPLL, wherein the control unit to adjust the loop bandwidth at speeds up to a sampling frequency for the filter.
16. The chip of claim 15 , wherein the one or more performance parameters of the DPLL includes at least one of: phase error or frequency error.
17. The chip of claim 15 , wherein the filter has a dominant pole that is greater than a dominant zero in the filter.
18. The chip of claim 15 , wherein the control unit to adjust the loop bandwidth by increasing loop bandwidth when the phase error increases.
19. The chip of claim 15 , wherein the control unit to adjust the loop bandwidth by reducing loop bandwidth when the phase error reduces.
20. A chip having a digital phase locked loop (DPLL), the chip comprising:
a filter for varying loop bandwidth of the DPLL when the DPLL is in operation, wherein the DPLL implements at least one of reference clock dithering or sigma-delta modulation; and
a control unit to monitor a scale and to adjust the loop bandwidth through control of the filter in response to one or more performance parameters of the DPLL being above or below the monitored scale, wherein the control unit to adjust the loop bandwidth at speeds up to a sampling frequency for the filter.
21. The chip of claim 20 , wherein the one or more performance parameters of the DPLL includes at least one of: phase error or frequency error.
22. A system comprising:
a processor including a digital phase locked loop (DPLL), the processor comprises:
a filter for varying loop bandwidth of the DPLL when the DPLL is in operation, wherein the DPLL implements at least one of reference clock dithering or sigma-delta modulation, and
a control unit to adjust the loop bandwidth through control of the filter according to a phase error, wherein the control unit to adjust the loop bandwidth at speeds up to a sampling frequency for the filter; and
a display unit for displaying information to a user.
23. The system of claim 22 , wherein the control unit to monitor a scale and to adjust the loop bandwidth through control of the filter in response to one or more performance parameters of the DPLL being above or below the monitored scale.
24. The system of claim 23 , wherein the one or more performance parameters of the DPLL includes at least one of: phase error or frequency error.
25. The system of claim 22 , wherein the DPLL is an all digital DPLL.
26. The system of claim 22 , wherein the filter is characterized by two or more coefficients which are controllably variable.
27. The system of claim 22 , wherein the filter has a dominant pole that is at least nine times greater than a dominant zero in the filter.
28. The system of claim 22 , wherein the control unit to adjust the loop bandwidth at speeds up to a sampling frequency for the filter.
29. The system of claim 22 , wherein the DPLL comprises:
a digital phase-frequency detector;
a digitally controlled oscillator; and
a divider.