Semiconducting device with stacked dice
View Patent ↗Some embodiments of the present invention relate to a semiconducting device and method that include a substrate and a first die that is attached to the substrate. The first die includes active circuitry (e.g., a flash memory array or logic circuitry) on an upper surface of the first die. The semiconducting device further includes a spacer that covers the active circuitry on the upper surface of the first die and a second die that is stacked onto the spacer and the first die. The spacer extends from a first side of the first die to an opposing second side of the first die. The spacer also extends near a third side of the first die and an opposing fourth side of the first die such that the active circuitry is exposed near the third and fourth sides of the first die.
1. A semiconducting device comprising:
a substrate;
a first die attached to the substrate, the first die including active circuitry on an upper surface;
a spacer covering the active circuitry on the upper surface of the first die, the spacer extending from a first side of the first die to an opposing second side of the first die and extending near a third side of the first die and an opposing fourth side of the first die such that the active circuitry is exposed near the third and fourth sides of the first die; and
a second die stacked onto the spacer and the first die,
wherein the spacer includes at least one section that extends to the third side of the first die such that the active circuitry is only partially exposed near the third side of the first die.
2. The semiconducting device of claim 1 , wherein the active circuitry on the upper surface of the first die includes a flash memory array.
3. The semiconducting device of claim 1 , wherein the spacer is attached to the upper surface of the first die using an adhesive.
4. The semiconducting device of claim 1 , wherein the spacer includes at least one section that extends to the fourth side of the first die such that the active circuitry is only partially exposed near the fourth side of the first die.
5. The semiconducting device of claim 1 , wherein the spacer is about 1 mm away from the third and fourth sides of the first die.
6. The semiconducting device of claim 1 , wherein the spacer is formed of silicon.
7. The semiconducting device of claim 1 , further comprising at least one additional die stacked onto the first die, the spacer and the second die.
8. The semiconducting device of claim 1 , further comprising at least one additional die mounted on the substrate, the first die being stacked onto the at least one additional die.
9. The semiconducting device of claim 1 , wherein the second die is attached to the spacer using an adhesive.
10. The semiconducting device of claim 1 , further comprising wires bonded to pads that are part of the exposed active circuitry near the third and fourth sides of the first die.
11. An electronic system comprising:
a buss;
a memory coupled to the buss; and
a semiconducting device that is electrically connected to the buss, the semiconducting device including a substrate and a flash memory that is attached to the substrate, the flash memory including active circuitry on an upper surface, the semiconducting device further including a spacer covering the active circuitry on the upper surface of the flash memory and a die that is stacked onto the spacer and the flash memory, the spacer extending from a first side of the flash memory to an opposing second side of the flash memory and wherein the spacer includes at least one section that extends to the third side of the flash memory such that the active circuitry is only partially exposed near the third side of the flash memory, the spacer further extending near an opposing fourth side of the flash memory such that the active circuitry is exposed near the fourth side of the flash memory.
12. The electronic system of claim 11 , wherein the spacer includes at least one section that extends to the fourth side of the flash memory such that the active circuitry is only partially exposed near the fourth side of the flash memory.
13. The electronic system of claim 11 , further comprising a voltage source electrically coupled to the semiconducting device.
14. The electronic system of claim 11 , further comprising wires bonded to pads that are part of the exposed active circuitry near the third and fourth sides of the flash memory, the wires being electrically coupled to the substrate.