IP Library Granted Patent US 10,096,080
Granted Patent B2
US 10,096,080 · App. 14/317,160 · Granted Oct 9, 2018

Power optimization with dynamic frame rate support

Inventors: Seh W. Kwa (Saratoga, CA); Nausheen Ansari (Folsom, CA); Satyanarayana Avadhanam (El Dorado Hills, CA)
Assignee: Intel Corporation
G06T1/20G06K9/00624G09G5/00G09G5/18G09G2330/022G09G2340/0435
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Quick Facts
Patent No.
US 10,096,080
App. No.
14/317,160
Granted
Oct 9, 2018
Kind
B2
Abstract

A frame of pixel data may be burst at a higher frame rate to create a lower effective refresh rate when the actual image update rate is lower than the frame rate. This results in the ability to power manage the transmit portion of the display engine and the receive portion of the panel electronics, while reducing display initiated repetitive memory traffic to conserve power.

Claims (38)

1. A method comprising:

detecting a first image frame that does not change from a previous second image frame;

in response to detecting the first image frame that did not change from the previous second image frame, lowering a refresh rate of a display to a lower refresh rate after sending the previous second image frame by refraining from sending the first image frame to the display;

causing a shutdown of a link to a display panel for a period that includes part of a vertical blanking interval and frame data time of the unsent first image frame, said period beginning after a hold time to account for a pipeline in the display and the period ending before a link training interval; and

power managing a display interface between a computer platform and the display panel during the link shutdown.

2. The method of claim 1 comprising sending a next changed frame to the display after the link shutdown.

3. The method of claim 1 comprising reading a register on the display panel to determine a link shutdown expiration time.

4. The method of claim 1 comprising increasing the length of the vertical blanking interval after the link shutdown.

5. The method of claim 4 comprising progressively decreasing the length of the vertical blanking interval, after resuming from the link shutdown, to send a changed image frame.

6. The method of claim 1 comprising changing the refresh rate, after the link shutdown when sending a changed image frame, to reduce flickering.

7. The method of claim 1 comprising reducing power consumption by reducing an effective refresh rate.

8. The method of claim 1 comprising sending image frames to the display panel without a panel frame buffer.

9. The method of claim 1 comprising waking an interface to send a changed image frame, and then reducing power consumption when an image frame is repeated.

10. One or more non-transitory computer readable media storing instructions executed by a processor to perform a sequence comprising:

detecting a first image frame that does not change from a previous second image frame;

in response to detecting the first image frame that did not change from the previous second image frame, lowering a refresh rate of a display to a lower refresh rate after sending the previous second image frame by refraining from sending the first image frame to the display;

causing a shutdown of a link to a display panel for a period that includes part of a vertical blanking interval and frame data time of the unsent first image frame, said period beginning after a hold time to account for a pipeline in the display and the period ending before a link training interval; and

power managing a display interface between a computer platform and the display panel during the link shutdown.

11. The media of claim 10 , said sequence comprising sending a next changed frame to the display after the link shutdown.

12. The media of claim 10 , said sequence comprising reading a register on the display panel to determine a link shutdown expiration time.

13. The media of claim 10 , said sequence comprising increasing the length of the vertical blanking interval after the link shutdown.

14. The media of claim 13 , said sequence comprising progressively decreasing the length of the vertical blanking interval, after resuming from the link shutdown, to send a changed image frame.

15. The media of claim 10 , said sequence comprising changing the refresh rate, after the link shutdown when sending a changed image frame, to reduce flickering.

16. An apparatus comprising:

a processor to:

detect a first image frame that does not change from a previous second image frame,

in response to detecting the first image frame that did not change from the previous second image frame, lower a refresh rate of a display to a lower refresh rate after sending the previous second image frame by refraining from the first image frame to the display,

cause a shutdown of a link to a display panel for a period that includes part of a vertical blanking interval and frame data time of the unsent first image frame, said period beginning after a hold time to account for a pipeline in the display and the period ending before a link training interval, and

power manage a display interface between a computer platform and the display panel during the link shutdown; and

a storage coupled to said processor.

17. The apparatus of claim 16 , said processor further to send a next changed frame to the display after the link shutdown.

18. The apparatus of claim 16 , said processor further to read a register on the display panel to determine a link shutdown expiration time.

19. The apparatus of claim 16 , said processor further to modify a vertical blanking interval length after the link shutdown.

20. The apparatus of claim 19 , said processor further to increase the length of the vertical blanking interval after the link shutdown.

21. The apparatus of claim 20 . said processor further to progressively decrease the length of the vertical blanking interval, after resuming from the link shutdown, to send a changed image frame.

22. The apparatus of claim 16 , said processor further to change the refresh rate, after the link shutdown when sending a changed image frame, to reduce flickering.

23. The apparatus of claim 16 further comprising a display communicatively coupled to the processor.

24. The apparatus of claim 16 further comprising a battery coupled to the processor.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2022
From: INTEL CORPORATION
To: TAHOE RESEARCH, LTD.
Reel/Frame 061175/0176 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2014
From: KWA, SEH W.; ANSARI, NAUSHEEN; AVADHANAM, SATYANARAYANA
To: INTEL CORPORATION
Reel/Frame 033342/0896 →
Continuity (1)
Related Publication 20150379665A1 · Dec 31, 2015
Cited By (2)
US 12,249,017 US 12,265,439