Power reducing logic and non-destructive latch circuits and applications
View Patent ↗In some embodiments, a logic circuit is provided that has a plurality of gates with gate inputs. Also provided is one or more latch circuits coupled to the logic circuit to provide operational data when in an operational mode and to cause at least some of the gate inputs to be at values resulting in reduced leakage during a sleep mode. Additionally provided are embodiments of non-destructive latch circuits, which may be used to implement the latch circuits just discussed. Other embodiments are disclosed and/or claimed herein.
1. A chip, comprising:
a logic circuit including combinational logic gates having gate inputs; and
one or more clocked latch circuits with data outputs coupled to the gate inputs to provide operational data when in an operational mode and to cause at least some of the gate inputs to be at predetermined values resulting in reduced leakage for the combinational logic gates during an inactive mode, wherein the one or more clocked latch circuits comprise non-destructive latch circuits, wherein data latched upon entry into a sleep mode is retained during the sleep mode.
2. The chip of claim 1 , in which the one or more clocked latch circuits comprise NOR gates to provide at least some of the data outputs.
3. The chip of claim 1 , in which the one or more clocked latch circuits comprise NAND gates to provide at least some of the data outputs.
4. The chip of claim 1 , in which the one or more clocked latch circuits comprise OR gates to provide at least some of the data outputs.
5. The chip of claim 1 , in which the one or more clocked latch circuits comprise AND gates to provide at least some of the data outputs.
6. An apparatus, comprising:
logic circuitry having data input nodes, said logic circuitry to be in at least one of a sleep mode and an operational mode; and
latch circuitry coupled to the logic circuitry data input nodes through at least one logic gate having first and second input nodes and an output node, the first input node coupled to a latch memory cell to hold a data value, the second input node coupled to a signal node for placing the logic circuitry into the sleep or operational mode, the output node coupled to the logic circuitry data input nodes to provide the data value during an operational mode and to provide a predetermined reduced leakage value during the sleep mode, the latch memory cell to retain a held data value during the sleep mode.
7. The apparatus of claim 6 , in which the latch circuitry includes a set latch.
8. The apparatus of claim 7 , in which the at least one logic gate comprises a NAND gate.
9. The apparatus of claim 8 , in which the latch circuitry comprises a cross-coupled pair of inverters.
10. The apparatus of claim 7 , in which the memory cell comprises a cross-coupled inverter pair.
11. A chip, comprising:
a circuit block having multiple data inputs to receive clocked sequential data values when in an operational mode and to receive a static, predetermined set of digital values for reduced leakage in the circuit block, during a sleep mode, wherein the sequential data and fixed predetermined values are from non-destructive latches, wherein data latched upon entry into a sleep mode is retained during the sleep mode.
12. The chip of claim 11 , in which the circuit block comprises logic in a processor core.
13. The chip of claim 11 , in which the fixed, predetermined set of digital values comprises both High and Low values.
14. The chip of claim 11 , in which the non-destructive latches comprise state retaining cells that are formed from cross-coupled inverter pairs.