Method of forming a semiconductor device with tall fins and using hard mask etch stops
View Patent ↗A hard mask etch stop is formed on the top surface of tall fins to preserve the fin height and protect the top surface of the fin from damage during etching steps of the transistor fabrication process. In an embodiment, the hard mask etch stop is formed using a dual hard mask system, wherein a hard mask etch stop layer is formed over the surface of a substrate, and a second hard mask layer is used to pattern a fin with a hard mask etch stop layer on the top surface of the fin. The second hard mask layer is removed, while the hard mask etch stop layer remains to protect the top surface of the fin during subsequent fabrication steps.
1. A method for forming a semiconductor device, comprising:
providing a substrate, wherein the substrate includes a monocrystalline semiconductor material;
blanket depositing a first hard mask layer over the substrate;
blanket depositing a second hard mask layer over the first hard mask layer;
etching the first hard mask layer and second hard mask layer to form a mask;
etching the substrate in alignment with the mask to form a fin;
blanket depositing a dielectric material over the fin;
polishing the dielectric material to be planar with a top surface of the first hard mask layer, wherein the second hard mask layer is removed in the polishing process;
etching the dielectric material to expose an active region of the fin;
blanket depositing a gate structure material; and
etching the gate structure material to form a gate structure, wherein the gate structure wraps around the fin to define a channel region within the fin and source/drain regions on opposite sides of the channel region, and wherein the first hard mask layer protects the top surface of the fin from the etching process.
2. The method of claim 1 , further comprising:
blanket depositing a sidewall spacer layer over the gate structure, the fin and the first hard mask layer;
etching the sidewall spacer layer to form gate sidewall spacers on sidewalls of the gate structure and fin sidewall spacers on the sidewalls of the fin, wherein the first hard mask layer protects the top surface of the fin during the etch process.
3. The method of claim 2 , further comprising:
etching the first hard mask layer to expose a top surface of the source/drain region of the fin; and
growing an epitaxial semiconductor layer from the top surface of the fin.
4. The method of claim 1 , further comprising:
blanket depositing an interlayer dielectric material over the gate structure and the fin;
polishing the interlayer dielectric material to expose the surface of the gate structure;
etching to remove the gate structure;
etching to remove the first hard mask layer to expose the top surface of the fin within the channel region;
depositing a gate dielectric layer within the channel region; and
depositing a gate electrode over the gate dielectric layer within the channel region.
5. The method of claim 4 , wherein depositing the gate electrode comprises:
depositing a work function metal layer; and
depositing a fill metal.
6. The method of claim 1 , further comprising:
etching to remove the first hard mask layer from the source/drain regions of the fin; and
forming source/drain contacts on the top surface of source/drain regions of the fin.
7. A method, comprising:
providing a substrate having a fin disposed thereon, wherein the fin has a base portion and an active portion, and wherein the active portion has a top surface and sidewall surfaces;
blanket depositing a dielectric material over the top surface of the fin;
polishing the dielectric material to expose the top surface of the fin;
etching to recess the top surface of the fin to form a trench;
blanket depositing a hard mask over the dielectric material and within the trench;
polishing the hard mask to be planar with the surface of the dielectric material;
etching the dielectric layer to exposing the sidewalls of the active portion of the fin;
blanket depositing a gate material over the fin;
etching the gate material to form a gate structure, wherein the gate structure wraps around the fin to define a channel region within the fin and source/drain regions on opposite sides of the channel region, and wherein the hard mask protects the top surface of the fin from the etching process.
8. The method of claim 7 , wherein depositing a hard mask comprises:
blanket depositing a first hard mask layer, wherein the first hard mask layer conforms to the trench; and
blanket depositing a sacrificial material over the first hard mask layer.
9. The method of claim 7 , further comprising:
blanket depositing a sidewall spacer layer over the gate structure, the fin and the hard mask;
etching the sidewall spacer layer to form gate sidewall spacers on sidewalls of the gate structure and fin sidewall spacers on the sidewalls of the fin, wherein the hard mask protects the top surface of the fin during the etch process.
10. The method of claim 9 , further comprising:
etching the hard mask to expose the top surface of the source/drain region of the fin; and
growing an epitaxial semiconductor layer from the top surface of the fin.
11. The method of claim 7 , further comprising:
blanket depositing an interlayer dielectric material over the gate structure and the fin;
polishing the interlayer dielectric material to expose the surface of the gate structure;
etching to remove the gate structure;
etching to remove the hard mask to expose the top surface of the fin within the channel region;
depositing a gate dielectric layer within the channel region; and
depositing a gate electrode over the gate dielectric layer within the channel region.
12. The method of claim 7 , further comprising:
etching to remove the hard mask from the source/drain regions of the fin; and
forming source/drain contacts on the top surface of source/drain regions of the fin.