Performing power management in a multicore processor

1. A processor comprising:

a plurality of first cores to independently execute instructions, each of the plurality of first cores including a first characterization circuit to measure performance characteristic information for one or more threads that execute on the first plurality of cores;

a plurality of second cores to independently execute instructions, each of the plurality of second cores including a second characterization circuit to measure performance characteristic information for one or more threads that execute on the second plurality of cores, wherein the plurality of second cores are heterogenous with respect to memory access as compared to the plurality of first cores; and

a controller to receive the performance characteristic information from at least some of the plurality of first cores, classify a workload type of a first thread based at least in part on the performance characteristic information to obtain trained model parameters, and based on the workload type classification and the trained model parameters, dynamically migrate the first thread from one or more of the plurality of first cores to one or more of the plurality of second cores.

2. The processor of claim 1 , wherein the controller is to dynamically migrate the first thread when the workload type classification is determined to be a memory bound workload.

3. The processor of claim 1 , wherein the plurality of second cores are optimized for a memory-bounded workload.

4. The processor of claim 1 , further comprising a power controller, wherein the power controller is to control power consumption of the processor using dynamic voltage frequency scaling.

5. The processor of claim 1 , wherein the processor further comprises at least one graphics processor.

6. The processor of claim 5 , wherein the processor further comprises a security coprocessor.

7. The processor of claim 1 , wherein the processor comprises a plurality of domains, including at least one core domain, at least one graphics domain, and an interconnect domain, wherein at least the core domain and the interconnect domain are to operate at different operating frequencies.

8. The processor of claim 1 , further comprising a plurality of voltage regulators, wherein each of the plurality of voltage regulators is associated with at least one of the plurality of first cores and the plurality of second cores.

9. The processor of claim 1 , wherein the plurality of second cores each include a first plurality of hardware thread resources, a number of the first plurality of hardware thread resources equal to a number of hardware thread resources of the plurality of first cores collectively, wherein each of the plurality of first cores comprises X hardware thread resources, Y is a number of the plurality of first cores, and a product of X×Y is the number of the first plurality of hardware thread resources.

10. The processor of claim 1 , wherein the controller comprises a machine learning controller.

11. The processor of claim 10 , wherein the machine learning controller is to perform self-learning during a lifetime of the processor.

12. A non-transitory machine-readable medium having stored thereon data, which if used by at least one machine, causes the at least one machine to fabricate at least one integrated circuit to perform a method comprising:

determining, via a migration logic of a processor, a classification of a workload executing on the processor based on performance metric information including memory latency information and memory bandwidth information received from a plurality of first cores of the processor, the processor comprising the plurality of first cores, a plurality of second cores and at least one memory controller, wherein the plurality of second cores are heterogenous with respect to memory access as compared to the plurality of first cores; and

migrating, via the migration logic, one or more threads from the plurality of first cores to the plurality of second cores based at least in part on the performance metric information, to reduce a level of at least one of memory latency and memory bandwidth for the one or more threads.

13. The non-transitory machine-readable medium of claim 12 , wherein the method further comprises dynamically migrating the one or more threads during execution of the one or more threads.

14. The non-transitory machine-readable medium of claim 12 , wherein the method further comprises migrating the one or more threads transparently to an operating system that executes on the processor.

15. A system comprising:

a multicore processor comprising:

a plurality of first cores to independently execute instructions, each of the plurality of first cores including a first characterization circuit to measure performance characteristic information for one or more threads that execute on the first plurality of cores;

a plurality of second cores to independently execute instructions, each of the plurality of second cores including a second characterization circuit to measure performance characteristic information for one or more threads that execute on the second plurality of cores, wherein the plurality of second cores are heterogenous with respect to memory access as compared to the plurality of first cores; and

a controller to receive the performance characteristic information from at least some of the plurality of first cores, classify a workload type of a first thread based at least in part on the performance characteristic information to obtain trained model parameters, and based on the workload type classification and the trained model parameters, dynamically migrate the first thread from one or more of the plurality of first cores to one or more of the plurality of second cores; and

a dynamic random access memory (DRAM) coupled to the processor.

16. The system of claim 15 , wherein the controller is to migrate a memory bounded workload from the plurality of first cores to the plurality of second cores.

17. The system of claim 15 , further comprising a power controller, wherein the power controller is to control power consumption of the multicore processor using dynamic voltage frequency scaling.

18. The system of claim 15 , wherein the controller comprises a machine learning controller to update one or more of the trained model parameters based at least in part on actual usage of the processor.

19. The system of claim 15 , wherein the plurality of second cores each include a first plurality of hardware thread resources, a number of the first plurality of hardware thread resources equal to a number of hardware thread resources of the plurality of first cores collectively, wherein each of the plurality of first cores comprises X hardware thread resources, Y is a number of the plurality of first cores, and a product of X×Y is the number of the first plurality of hardware thread resources.