Processor having accelerated user responsiveness in constrained environment
In one embodiment, a processor includes at least one core to execute instructions and a power controller coupled to the at least one core. The power controller may include a first logic to cause the at least one core to exit an idle state and enter into a maximum performance state for a first time duration, thereafter enter into an intermediate power state for a second time duration, and thereafter enter into a sustained performance state. Other embodiments are described and claimed.
1. A processor comprising:
a memory controller to couple the processor to a memory device;
a first plurality of cores to execute instructions;
a second plurality of cores to execute instructions;
a graphics processor to execute graphics commands;
an input/output (IO) interface to couple to one or more IO devices;
an interconnect fabric to couple the first and second plurality of cores, the graphics processor, and the IO interface to the memory controller;
a multimedia processor to perform capture and playback of high definition video and audio content;
a display controller to provide control of and an interface to an associated display; and
a security processor to perform security operations including cryptography operations; and
a power controller including hardware logic to manage power consumption of the plurality of cores, the hardware logic to:
cause at least one core to operate at one or more intermediate power levels between a first power level and a second power level;
wherein the first power level is greater than the second power level,
wherein the first power level corresponds to a maximum power level requestable by an operating system, and the second power level corresponds to a maximum sustainable power level requestable by the operating system; and
wherein the one or more intermediate power levels and/or a duration of time at which to operate the at least one core at the one or more intermediate power levels is determined based on a system skin temperature.
2. The processor of claim 1 wherein the maximum sustainable power level corresponds to a maximum guaranteed performance level.
3. The processor of claim 1 wherein the first power level corresponds to a maximum performance level requestable by the operating system.
4. The processor of claim 1 wherein the power controller is to cause the at least one core to enter into the first power level from an idle state.
5. The processor of claim 4 wherein the duration of time comprises a first duration of time and wherein the power controller is to cause the at least one core to operate at the first power level for a second duration of time before operating at the one or more intermediate power levels.
6. The processor of claim 5 wherein the second duration of time is based on a power budget, thermal budget, or timer.
7. The processor of claim 1 wherein the maximum power level requestable by the operating system is a P0 state or turbo boost state.
8. The processor of claim 1 further comprising:
a sensor unit comprising a sensor controller to interface to one or more off-chip sensors to provide the system skin temperature.
9. The processor of claim 1 wherein the security processor is further to perform the security operations including secure boot operations.
10. The processor of claim 1 , wherein the one or more intermediate power levels between the first power level and the second power level comprise a plurality of intermediate power levels.
11. The processor of claim 1 wherein the system skin temperature is to be measured from an outer surface of a computing system in which the processor is configured.
12. The processor of claim 1 wherein the first power level, the second power level, and the one or more intermediate power levels are each associated with a different frequency and/or voltage.
13. The processor of claim 12 wherein each core of the plurality of cores operates at an independent voltage and frequency from other cores of the plurality of cores.
14. A processor comprising:
a memory controller to couple the processor to a memory device;
a first plurality of cores to execute instructions;
a second plurality of cores to execute instructions;
a graphics processor to execute graphics commands;
an input/output (IO) interface to couple to one or more IO devices;
an interconnect fabric to couple the first and second plurality of cores, the graphics processor, and the IO interface to the memory controller;
a multimedia processor to perform capture and playback of high definition video and audio content;
a display controller to provide control of and an interface to an associated display; and
a security processor to perform security operations including cryptography operations; and
a power controller including hardware logic to manage power consumption of the plurality of cores, the hardware logic to:
cause at least one core to operate at one or more intermediate clock frequencies between a first clock frequency and a second clock frequency;
wherein the first clock frequency is greater than the second clock frequency;
wherein the first clock frequency corresponds to a maximum performance state requestable by an operating system, and the second clock frequency corresponds to a maximum guaranteed performance state; and
wherein the one or more intermediate clock frequencies and/or a duration of time at which to operate the at least one core at the one or more intermediate clock frequencies is determined based on a system skin temperature.
15. The processor of claim 14 , wherein the maximum performance state requestable by the operating system corresponds to a turbo mode state or P0 state of the processor, and wherein the maximum guaranteed performance state corresponds to a maximum peak frequency of the processor stored or written into the processor during manufacture.
16. The processor of claim 14 wherein the power controller is to cause the at least one core to exit an idle state to operate at the first clock frequency.
17. The processor of claim 16 wherein the duration of time comprises a first duration of time and wherein the power controller is to cause the at least one core to operate at the first clock frequency for a second duration of time before operating at the one or more intermediate clock frequencies.
18. The processor of claim 16 wherein the second duration of time is based on a power budget, thermal budget, or timer.
19. The processor of claim 14 further comprising:
a sensor unit comprising a sensor controller to interface to one or more off-chip sensors to provide the system skin temperature.
20. The processor of claim 14 wherein the security processor is further to perform the security operations including secure boot operations.
21. The processor of claim 14 wherein the system skin temperature is to be measured from an outer surface of a computing system in which the processor is configured.
22. The processor of claim 21 wherein each core of the plurality of cores operates at an independent voltage and frequency from other cores of the plurality of cores.