IP Library Granted Patent US 10,804,188
Granted Patent B2
US 10,804,188 · App. 16/124,838 · Granted Oct 13, 2020

Electronic device including a lateral trace

Inventors: Yikang Deng (Chandler, AZ); Ying Wang (Chandler, AZ); Cheng Xu (Chandler, AZ); Chong Zhang (Chandler, AZ); Junnan Zhao (Gilbert, AZ)
Assignee: Intel Corporation
H01L23/49822H01L23/5383
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Quick Facts
Patent No.
US 10,804,188
App. No.
16/124,838
Granted
Oct 13, 2020
Kind
B2
Abstract

An electronic device may include a substrate, and the substrate may include one or more layers. The one or more layers may include a first dielectric material and one or more electrical traces. A cavity may be defined in the substrate, and the cavity may be adapted to receive one or more electrical components. One or more lateral traces may extend through a wall of the cavity. The lateral traces may provide electrical communication pathways between the substrate and the electrical components.

Claims (19)

1. An electronic device, comprising:

a substrate including one or more layers, the one or more layers including a first dielectric material and one or more electrical traces;

a first cavity defined in the substrate and adapted to receive one or more electrical components;

a second cavity defined in the substrate and adapted to receive the one or more electrical components;

a first lateral trace extending through a wall of the first cavity, wherein the first lateral trace is configured to provide electrical communication pathways between the substrate and the one or more electrical components;

a first semiconductor die positioned in the first cavity defined in the substrate, and wherein the first semiconductor die is embedded in the substrate;

a second semiconductor die positioned on a surface of the substrate, wherein the first semiconductor die and the second semiconductor die are in electrical communication through the substrate;

a third semiconductor die positioned in the second cavity defined in the substrate, and wherein the third semiconductor die is embedded in the substrate; and

wherein the first lateral trace extends through a wall of the second cavity, and the first lateral trace electrically interconnects the first semiconductor die and the third semiconductor die.

2. The electronic device of claim 1 , further comprising a second lateral trace extending through a wall of the second cavity, wherein the second lateral trace is configured to provide electrical communication pathways between the substrate and the one or more electrical components.

3. The electronic device of claim 1 , wherein a portion of the third semiconductor die is coplanar with a portion of the first semiconductor die.

4. The electronic device of claim 1 , wherein the first semiconductor die is positioned within a footprint of the second semiconductor die.

5. The electronic device of claim 1 , further comprising a first via coupled to a first side of the first semiconductor die, and a second via coupled to a second side of the first semiconductor die.

6. The electronic device of claim 1 , further comprising:

a via configured to facilitate the electrical communication between the one or more layers of the substrate; and

a second lateral trace in electrical communication with the via, wherein the second lateral trace extends perpendicular to the via.

7. The electronic device of claim 6 , wherein the via is positioned within a footprint of the first cavity.

8. The electronic device of claim 6 , wherein the second lateral trace is coplanar with a portion of a via.

9. The electronic device of claim 1 , further comprising a plurality of interconnects positioned in the first cavity and configured to couple with the first semiconductor die, and wherein one or more of the first lateral trace or a second lateral trace are in communication with at least one of the plurality of interconnects.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2022
From: INTEL CORPORATION
To: TAHOE RESEARCH, LTD.
Reel/Frame 061175/0176 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 12, 2018
From: DENG, YIKANG; WANG, YING; XU, CHENG; ZHANG, CHONG; ZHAO, JUNNAN
To: INTEL CORPORATION
Reel/Frame 046855/0989 →
Cited By (1)
US 12,463,178