Stiffener-integrated interconnect bypasses for chip-package apparatus and methods of assembling same

1. A semiconductor package frame stiffener, comprising:

a frame stiffener including a top surface and a die-side ledge that is opposite the top surface, further including a die-side interconnect surface that is opposite the top surface, and further including a land-side interconnect surface that is parallel planar with the die-side interconnect surface;

a through hole that communicates from the top surface to the die-side ledge, and from the top surface to the die-side interconnect surface;

an integrated cable-header recess that communicates to the top surface, wherein the integrated cable-header recess is adjacent to the die-side interconnect surface and adjacent to the land-side interconnect surface; and

a through-frame-stiffener interconnect (TFSI) including two or more electrical connections, that communicates from the land-side interconnect surface, through the frame stiffener and into the integrated cable-header recess.

2. The semiconductor package frame stiffener of claim 1 , further including a cable header electrically coupled to the TFSI.

3. The semiconductor package frame stiffener of claim 1 , further including:

a cable header electrically coupled to the TFSI; and

a flexible cable coupled to the cable header.

4. The semiconductor package frame stiffener of claim 1 , further including:

a cable header electrically coupled to the TFSI;

a flexible cable coupled to the cable header;

a passive device opposite the integrated cable-header recess, wherein the passive device is coupled to a folded redistribution layer at the land-side interconnect surface;

a semiconductor package substrate including a die side and a land side, wherein the die side is in contact with the die-side ledge; and

a semiconductive device on the die side, wherein the semiconductive device is coupled to the TFSI through a folded redistribution layer that contacts the land-side interconnect surface and the die-side interconnect surface.

5. The semiconductor package frame stiffener of claim 1 , further including a passive device opposite the integrated cable-header recess, wherein the passive device is coupled to a folded redistribution layer at the land-side interconnect surface.

6. The semiconductor package frame stiffener of claim 1 , further including:

a cable header electrically coupled to the TFSI;

a semiconductor package substrate including a die side and a land side, wherein the die side is in contact with the die-side ledge; and

a semiconductive device on the die side, wherein the semiconductive device is coupled to the TFSI through a folded redistribution layer that contacts the land-side interconnect surface and the die-side interconnect surface.

7. The semiconductor package frame stiffener of claim 1 , further including:

a cable header electrically coupled to the TFSI;

a semiconductor package substrate including a die side and a land side, wherein the die side is in contact with the die-side ledge;

a semiconductive device on the die side, wherein the semiconductive device is coupled to the TFSI through a folded redistribution layer that contacts the land-side interconnect surface and the die-side interconnect surface; and

a first stacked semiconductive device on the semiconductive device, wherein the first stacked semiconductive device is coupled to the semiconductive device by a through-silicon via.

8. The semiconductor package frame stiffener of claim 1 , further including a folded redistribution layer (fRDL) that is coupled to the frame stiffener opposite the integrated cable-header recess at the land-side interconnect surface, and wherein the fRDL is also coupled opposite the top surface at the die-side interconnect surface.

9. The semiconductor package frame stiffener of claim 1 , further including a semiconductor package substrate that, includes a die side and a land side, wherein the frame stiffener contacts the semiconductor package substrate at the die-side ledge.

10. The semiconductor package frame stiffener of claim 1 , further including:

a folded redistribution layer (fRDL) that is coupled to the frame stiffener opposite the integrated cable-header recess at the land-side interconnect surface, and wherein the fRDL is also coupled opposite the top surface at, the die-side interconnect surface; and

a semiconductor package substrate that includes a die side and a land side, wherein the frame stiffener contacts the semiconductor package substrate at the die-side ledge, and wherein the fRDL is coupled to the die side by a trace within the semiconductor package substrate.

11. The semiconductor package frame stiffener of claim 1 , further including:

a folded redistribution layer (fRDL) that is coupled to the frame stiffener opposite the integrated cable-header recess at the land-side interconnect surface, and wherein the fRDL is also coupled opposite the top surface at, the die-side interconnect surface; and

a semiconductor package substrate that includes a die side and a land side, wherein the frame stiffener is coupled to the semiconductor package substrate through the fRDL at the die-side interconnect surface.

12. The semiconductor package frame stiffener of claim 1 , further including:

a folded redistribution layer (fRDL) that is coupled to the frame stiffener opposite the integrated cable-header recess at the land-side interconnect surface, and wherein the fRDL is also coupled opposite the top surface at the die-side interconnect surface;

a semiconductor package substrate that includes a die side and a land side, wherein the frame stiffener contacts the semiconductor package substrate at the die-side ledge; and

wherein the frame stiffener is coupled to the semiconductor package substrate through the fRDL at the die-side interconnect surface.

13. The semiconductor package frame stiffener of claim 1 , further including:

a folded redistribution layer (fRDL) that is coupled to the frame stiffener opposite the integrated cable-header recess at the land-side interconnect surface, and wherein the fRDL is also coupled opposite the top surface at the die-side interconnect surface;

a semiconductor package substrate that includes a die side and a land side, wherein the frame stiffener contacts the semiconductor package substrate at the die-side ledge;

wherein the frame stiffener is coupled to the semiconductor package substrate through the fRDL at the die-side interconnect surface; and

a semiconductive device disposed on the die side, wherein the semiconductive device is coupled to the fRDL at the die-side interconnect surface, through a trace in the semiconductor package substrate.

14. The semiconductor package frame stiffener of claim 13 , wherein the integrated cable-header recess is a first integrated cable-header recess and wherein the fRDL is a first fRDL, further including:

a semiconductor package substrate that includes a die side and a land side, wherein the frame stiffener contacts the semiconductor package substrate at the die-side ledge, and wherein the first fRDL, is coupled to the die side by a first trace within the semiconductor package substrate;

a subsequent integrated cable-header recess that communicates to the top surface, wherein the subsequent integrated cable-header recess is adjacent to a subsequent die-side interconnect surface and adjacent to a subsequent land-side interconnect surface;

a subsequent through-frame-stiffener interconnect (TFSI) that communicates from the subsequent land-side interconnect surface, through the frame stiffener and into the subsequent integrated cable-header recess; and

a subsequent fRDL coupled to the die side by a subsequent trace within the semiconductor package substrate.

15. The semiconductor package frame stiffener of claim 1 , wherein the integrated cable-header recess is a first integrated cable-header recess, further including a subsequent cable-header recess that communicates to the top surface.

16. The semiconductor package frame stiffener of claim 1 , wherein the integrated cable-header recess is a first integrated cable-header recess, wherein the land-side interconnect surface is a first land-side interconnect surface, and wherein the die-side interconnect surface is a first die-side interconnect surface, further including:

a first folded redistribution layer (fRDL) that is coupled to the frame stiffener opposite the first integrated cable-header recess at the first land-side interconnect surface, and wherein the first fRDL, is also coupled opposite the top surface at the first die-side interconnect surface;

a subsequent cable-header recess that communicates to the top surface;

a subsequent folded redistribution layer (fRDL) that is coupled to the frame stiffener opposite the subsequent integrated cable-header recess at the subsequent land-side interconnect surface, and wherein the subsequent fRDL is also coupled opposite the top surface at the subsequent die-side interconnect surface;

a first semiconductive device disposed on the die side, wherein the first semiconductive device is coupled to the first fRDL, at the first die-side interconnect surface, through a first trace in the semiconductor package substrate; and

a subsequent semiconductive device disposed on the die side, wherein the subsequent semiconductive device is coupled to the subsequent fRDL at the subsequent die-side interconnect surface, through a subsequent trace in the semiconductor package substrate.

17. The semiconductor package frame stiffener of claim 1 , wherein the TFSI is a cable-header TFSI, further including:

a cable header electrically coupled to the cable-header TFSI;

a semiconductor package substrate including a die side and a land side, wherein the die side is in contact with the die-side ledge;

a semiconductive device on the die side, wherein the semiconductive device is coupled to the cable-header TFSI through a folded redistribution layer that contacts the land-side interconnect surface and the die-side interconnect surface;

a package-on-package (POP) TFSI that communicates from the die-side ledge to the top surface; and

a POP module coupled to the POP TFSI at the top surface.

18. A method of assembling a frame stiffener, comprising:

forming a through hole in a blank;

forming a die-side ledge in the blank, wherein the die-side ledge is opposite a top surface forming an integrated cable-header recess adjacent the through hole, wherein the integrated cable-header recess is defined by a die-side interconnect surface and a land-side interconnect surface, and wherein the integrated cable-header recess communicates to the top surface;

forming a through-frame-stiffener interconnect (TFSI) including two or more electrical connections, in the integrated cable-header recess to communicate to the land-side surface.

19. The method of claim 18 , further including:

assembling a folded redistribution layer (fRDL) to the die-side interconnect surface and to the land-side interconnect surface; and

coupling the fRDL to the TFSI.

20. The method of claim 18 , further including:

assembling a folded redistribution layer (fRDL) to the die-side interconnect surface and to the land-side interconnect surface;

coupling the fRDL to the TFSI;

seating a semiconductor package substrate to the die-side ledge; and

coupling the fRDL to the semiconductor package substrate by a trace within the semiconductor package substrate.

21. A computing system, comprising:

a semiconductive die disposed on a semiconductor package substrate;

a frame stiffener including a top surface and a die-side ledge that is opposite the top surface, further including a die-side interconnect surface that is opposite the top surface, and further including a land-side interconnect surface that, is parallel planar with the die-side interconnect surface;

wherein the semiconductor package substrate contacts the die-side ledge;

a through hole that communicates from the top surface to the die-side ledge, and from the top surface to the die-side interconnect surface;

an integrated cable-header recess that communicates to the top surface, wherein the integrated cable-header recess is adjacent to the die-side interconnect surface and adjacent to the land-side interconnect surface;

wherein the semiconductor package substrate is coupled to the integrated cable-header recess through a folded redistribution layer that contacts the die-side interconnect surface;

a through-frame-stiffener interconnect (TFSI) that communicates from the land-side interconnect surface, through the frame stiffener and into the integrated cable-header recess the die side; and

a board at which the land side is mounted by at least one electrical bump, and wherein the board includes a dielectric outer shell.

22. The computing system of claim 21 , further including:

wherein the semiconductive device is part of a chipset.