IP Library › Granted Patent US 9,829,965
Granted Patent B2
US 9,829,965 · App. 14/498,014 · Granted Nov 28, 2017

Distribution of tasks among asymmetric processing elements

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Quick Facts
Patent No.
US 9,829,965
App. No.
14/498,014
Granted
Nov 28, 2017
Kind
B2
Abstract

Techniques are disclosed to control power and processing among a plurality of asymmetric cores. In one embodiment, a multi-core processor includes first and second processing cores, each including an arithmetic logic unit and an instruction decoder, wherein the first processing core is capable of operating at a higher processing throughput than the second processing core, wherein the first and second processing cores have different instruction sets, wherein, in response to an occurrence of an event, a task processed on the first processing core is to be translated and transferred to the second processing core after saving a core state of the first processing core and providing the core state to the second processing core, wherein instructions to run on the second processing core are translated to the instruction set of the second processing core by a software binary translation shell, and wherein the first and second processing cores are to concurrently execute instructions according to their own instruction sets.

Claims (33)

1. A multi-core processor comprising:

a first processing core and a second processing core, each including one or more arithmetic logic units and an instruction decoder; wherein the first processing core is capable of operating at a higher processing throughput than that of the second processing core, wherein the first and second processing cores have different instruction sets;

wherein, in response to an occurrence of an event, a task processed on the first processing core is to be translated and transferred from the first processing core to the second processing core after saving a core state of the first processing core and providing the core state to the second processing core; and

wherein instructions to run on the second processing core are to be translated from the instruction set of the first processing core to the instruction set of the second processing core by a software binary translation shell, wherein the first processing core and the second processing core are to concurrently execute instructions, each according to its own instruction set.

2. The multi-core processor of claim 1 , wherein the higher processing throughput is based on a first pipeline depth of the first processing core that is greater than a pipeline depth of the second processing core.

3. The multi-core processor of claim 1 , wherein the higher processing throughput is based on a power consumption of the first processing core that is greater than a power consumption of the second processing core.

4. The multi-core processor of claim 1 , wherein one of the instruction sets is a complex instruction set computing instruction set and the other of the instruction sets is a reduced instruction set computing instruction set.

5. A method comprising:

translating and transferring, in a processor comprising a first processing core and a second processing core, each including one or more arithmetic logic units and an instruction decoder, wherein the first processing core is capable of operating at a higher processing throughput than that of the second processing core, and wherein the first and second processing cores have different instruction sets, a task processed on the first processing core to the second processing core after saving a core state of the first processing core and providing the core state to the second processing core, in response to an occurrence of an event;

wherein instructions to run on the second processing core are to be translated from the instruction set of the first processing core to the instruction set of the second processing core by a software binary translation shell, wherein the first processing core and the second processing core are to concurrently execute instructions, each according to its own instruction set.

6. The method of claim 5 , wherein the higher processing throughput is based on a first pipeline depth of the first processing core that is greater than a pipeline depth of the second processing core.

7. The method of claim 5 , wherein the higher processing throughput is based on a power consumption of the first processing core that is greater than a power consumption of the second processing core.

8. The method of claim 5 , wherein one of the instruction sets is a complex instruction set computing instruction set and the other of the instruction sets is a reduced instruction set computing instruction set.

9. A system comprising:

a graphics processor; a memory controller; peripheral control circuitry; and a multi-core processor coupled to the graphics processor, the memory controller, and the peripheral control circuitry, the multi-core processor including, a first processing core and a second processing core, each including one or more arithmetic logic units and an instruction decoder, wherein the first and second processing cores have different instruction sets;

wherein the first processing core is capable of operating at a higher processing throughput than that of the second processing core;

wherein, in response to an occurrence of an event, a task processed on the first processing core is to be translated and transferred from the first processing core to the second processing core after saving a core state of the first processing core and providing the core state to the second processing core; and

wherein instructions to run on the second processing core are to be translated from the instruction set of the first processing core to the instruction set of the second processing core by a software binary translation shell, wherein the first processing core and the second processing core are to concurrently execute instructions, each according to its own instruction set.

10. The system of claim 9 , wherein the higher processing throughput is based on a first pipeline depth of the first processing core that is greater than a pipeline depth of the second processing core.

11. The system of claim 9 , wherein the higher processing throughput is based on a power consumption of the first processing core that is greater than a power consumption of the second processing core.

12. The system of claim 9 , wherein one of the instruction sets is a complex instruction set computing instruction set and the other of the instruction sets is a reduced instruction set computing instruction set.

13. A system comprising:

a graphics processor;

a memory controller;

peripheral control circuitry;

a multi-core processor coupled to the graphics processor, the memory controller, and the peripheral control circuitry, the multi-core processor including a first processing core and a second processing core, each including one or more arithmetic logic units and an instruction decoder, wherein the first processing core is capable of operating at a higher processing throughput than that of the second processing core, wherein the first and second processing cores have different instruction sets;

wherein, in response to an occurrence of an event, a task processed on the first processing core is to be translated and transferred from the first processing core to the second processing core after saving a core state of the first processing core and providing the core state to the second processing core; and

wherein instructions to run on the second processing core are to be translated from the instruction set of the first processing core to the instruction set of the second processing core by a software binary translation shell, wherein the first processing core and the second processing core are to concurrently execute instructions, each according to its own instruction set.

14. The system of claim 13 , wherein the higher processing throughput is based on a first pipeline depth of the first processing core that is greater than a pipeline depth of the second processing core.

15. The system of claim 13 , wherein the higher processing throughput is based on a power consumption of the first processing core that is greater than a power consumption of the second processing core.

16. The system of claim 13 , wherein one of the instruction sets is a complex instruction set computing instruction set and the other of the instruction sets is a reduced instruction set computing instruction set.

17. The system of claim 13 , wherein the first processing core and the second processing core are to concurrently execute instructions according to their own instruction sets.

18. The system of claim 17 , wherein the first processing core and the second processing core operate at different voltage levels, different instruction throughputs, different power consumption rates, different clock frequencies, and different pipeline depths.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2022
From: INTEL CORPORATION
To: TAHOE RESEARCH, LTD.
Reel/Frame 061175/0176 →