Stress in trigate devices using complimentary gate fill materials
View Patent ↗Embodiments relate to an improved tri-gate device having gate metal fills, providing compressive or tensile stress upon at least a portion of the tri-gate transistor, thereby increasing the carrier mobility and operating frequency. Embodiments also contemplate method for use of the improved tri-gate device.
1. A semiconductor device, comprising:
a first channel comprising an N-type material raised above a substrate, the first channel having a first top surface, a first pair of sidewalls, and a first current flow direction along a first major axis of the first channel;
a second channel comprising a P-type material raised above the substrate, the second channel having a second top surface, a second pair of sidewalls, and a second current flow direction along a second major axis of the second channel;
a first gate wrapped around the first top surface and the first pair of sidewalls of the first channel, wherein the first gate comprises a first metal fill that exerts a tensile stress upon the first channel such that charge carrier mobility in the first channel is improved in the first current flow direction; and
a second gate wrapped around the second top surface and the second pair of sidewalls of the second channel, wherein the second gate comprises a second metal fill that exerts a compressive stress upon the second channel such that charge carrier mobility in the second channel is improved in the second current flow direction,
wherein the first metal fill and the second metal fill are different metals.
2. The semiconductor device of claim 1 , wherein the first gate has a depth of 10-100 nm.
3. The semiconductor device of claim 1 , wherein the second gate has a depth of 10-100 nm.
4. The semiconductor device of claim 1 , wherein the tensile stress exerted upon the first channel is substantially unequal to the compressive stress exerted upon the second channel.
5. The semiconductor device of claim 1 , wherein the first metal fill comprises copper.
6. The semiconductor device of claim 1 , wherein the second metal fill comprises tungsten.
7. The semiconductor device of claim 1 , wherein the first metal fill comprises copper, and the second metal fill comprises tungsten.
8. The semiconductor device of claim 1 , wherein the substrate is a bulk silicon substrate.
9. The semiconductor device of claim 1 , wherein the substrate is a silicon on insulator (SOI) substrate.
10. The semiconductor device of claim 1 , wherein the first gate is substantially perpendicular to the first major axis.
11. The semiconductor device of claim 1 , wherein the second gate is substantially perpendicular to the second major axis.