Performance enhancement of address translation using translation tables covering large address spaces
An embodiment of the present invention is a technique to enhance address translation performance. A register stores capability indicators to indicate capability supported by a circuit in a chipset for address translation of a guest physical address to a host physical address. A plurality of multi-level page tables is used for page walking in the address translation. Each of the page tables has page table entries. Each of the page table entries has at least an entry specifier corresponding to the capability indicated by the capability indicators.
1 . An apparatus, comprising:
an enable register to enable logic to translate a direct memory access (DMA) guest physical address to a given host physical address; and
a multi-level tree structure of page tables to store a plurality of directory entries in one or more non-bottom level page tables, wherein each directory entry points to a lower level page table in the tree structure, and
store a plurality of host physical addresses in one or more bottom level page tables in the tree structure;
wherein the logic is operable to utilize the tree structure for translation purposes to map the DMA guest physical address to the given host physical address.
2 . The apparatus of claim 1 , further comprising:
a base address register to store a base address of a root page table, the root page table comprising a top page table of the multi-level tree structure.
3 . The apparatus of claim 1 , further comprising:
a capability register to store a maximum supported size of the guest physical address.
4 . The apparatus of claim 1 , further comprising:
a capability register to store a coherency control bit, wherein when the bit is set the logic will snoop the translated host physical address if a coherency field is asserted in the page table entry associated with the translated host physical address.
5 . A method, comprising:
storing a plurality of directory entries in one or more non-bottom level page tables within a multi-level tree structure of page tables, wherein each directory entry points to a lower level page table in the tree structure;
storing a plurality of host physical addresses in one or more bottom level page tables within the tree structure of page tables; and
mapping a direct memory access (DMA) guest physical address to a given host physical address by utilizing the tree structure.
6 . The method of claim 5 , further comprising:
setting an enable register in a computer system to enable logic within the computer system to translate the DMA guest physical address to the given host physical address through the mapping.
7 . The method of claim 5 , further comprising:
storing a base address of a root page table in a base address register in the computer system, the root page table comprising a top page table of the multi-level tree structure.
8 . The method of claim 5 , further comprising:
storing a maximum supported size of the guest physical address in a capability register in the computer system.
9 . The method of claim 5 , further comprising:
snooping the translated host physical address if a coherency control bit is set in a capability register in the computer system and a coherency field is asserted in the page table entry associated with the translated host physical address.