SRAM with forward body biasing to improve read cell stability
View Patent ↗A SRAM memory cell comprising cross-coupled inverters, each cross-coupled inverter comprising a pull-up transistor, where the pull-up transistors are forward body biased during read operations. Forward body biasing improves the read stability of the memory cell. Other embodiments are described and claimed.
1. A memory cell comprising:
a first inverter comprising a first pull-up transistor, the first pull-up transistor comprising a first body terminal;
a second inverter cross-coupled to the first inverter and comprising a second pull-up transistor comprising a second body terminal; and
a switch connected to the first and second body terminals, the switch coupling the first and the second body terminals to a forward body bias voltage.
2. The memory cell as set forth in claim 1 , the memory cell further comprising a power rail and a ground rail, wherein
the first pull-up transistor of the first inverter is a first pFET, further comprising a first source terminal connected to the power rail, a first gate terminal, and a first drain terminal;
the first inverter further comprises a first pull-down nFET comprising a second drain terminal connected to the first drain terminal of the first pFET of the first inverter, comprising a second gate terminal, and comprising a second source terminal connected to the ground rail;
the second pull-up transistor of the second inverter is a second pFET, further comprising a third source terminal connected to the power rail, a third gate terminal, and a third drain terminal;
the second inverter further comprises a second pull-down NFET comprising a fourth drain terminal connected to the third drain terminal of the second pFET of the second inverter, comprising a fourth gate terminal, and comprising a fourth source terminal connected to the ground rail; and
wherein the first and second gates of the first pFET and the first NFET, respectively of the first inverter are connected to the third drain of the second pFET of the second inverter, and the third and fourth gates of the second pFET and the second nFET, respectively, of the second inverter are connected to the first drain of the first pFET of the first inverter.
3. A memory cell comprising:
a first inverter comprising a first pull-up transistor, the first pull-up transistor comprising a first body; and
a second inverter cross-coupled to the first inverter and comprising a second pull-up transistor comprising a second body;
wherein the first and second bodies are forward biased.
4. The memory cell as set forth in claim 3 , the memory cell further comprising a power rail and a ground rail, wherein
the first pull-up transistor of the first inverter is a first pFET, further comprising a first source terminal connected to the power rail, a first gate terminal, and a first drain terminal;
the first inverter further comprises a first pull-down nFET comprising a second drain terminal connected to the first drain terminal of the first pFET of the first inverter, comprising a second gate terminal, and comprising a second source terminal connected to the ground rail;
the second pull-up transistor of the second inverter is a second pFET, further comprising a third source terminal connected to the power rail, a third gate terminal, and a third drain terminal;
the second inverter further comprises a second pull-down NFET comprising a fourth drain terminal connected to the third drain terminal of the second pFET of the second inverter, comprising a fourth gate terminal, and comprising a fourth source terminal connected to the ground rail; and
wherein the first and second gates of the first pFET and the first NFET, respectively, of the first inverter are connected to the third drain of the second pFET of the second inverter, and the third and fourth gates of the second pFET and the second nFET, respectively, of the second inverter are connected to the first drain of the first pFET of the first inverter.
5. A memory comprising:
a cell comprising:
a first inverter comprising a first pull-up transistor comprising a first body terminal and a first source terminal; and
a second inverter comprising a second pull-up transistor comprising a second body terminal and a second source terminal, wherein the first and second inverters are cross-coupled to each other;
wherein the first and second source terminal are coupled to a power rail, the power rail having a voltage Vcc; and
wherein the first and second body terminals are coupled to a bias voltage generator, the bias voltage generator having a voltage Vb, wherein Vb<Vcc.
6. The memory as set forth in claim 5 , further comprising:
a switch coupling the voltage Vb of the bias voltage generator to the first and second body terminals during a read operation on the memory cell.
7. The memory as set forth in claim 6 , the memory comprising a ground rail, the ground rail having a voltage Vss, where Vss<Vb, wherein
the first pull-up transistor of the first inverter is a first pFET, further comprising a first gate terminal and a first drain terminal;
the first inverter further comprises a first pull-down NFET comprising a second drain terminal connected to the first drain terminal of the first pFET of the first inverter, the first pull-down nFET comprising a second gate terminal, and comprising a second source terminal connected to the ground rail;
the second pull-up transistor of the second inverter is a second pFET, further comprising a third gate terminal and a third drain terminal;
the second inverter further comprises a second pull-down NFET comprising a fourth drain terminal connected to the third drain terminal of the second pFET of the second inverter, comprising a fourth gate terminal, and comprising a fourth source terminal connected to the ground rail; and
wherein the first and second gates of the first pFET and the first nFET, respectively, of the first inverter are connected to the third drain of the second pFET of the second inverter, and the third and fourth gates of the second pFET and the second NFET, respectively, of the second inverter are connected to the first drain of the first pFET of the first inverter.
8. The memory as set forth in claim 5 , the memory comprising a ground rail, the ground rail having a voltage Vss, where Vss<Vb, wherein
the first pull-up transistor of the first inverter is a first pFET, further comprising a first gate terminal and a first drain terminal;
the first inverter further comprises a first pull-down nFET comprising a second drain terminal connected to the first drain terminal of the first pFET of the first inverter, the first pull-down nFET comprising a second gate terminal, and comprising a second source terminal connected to the ground rail;
the second pull-up transistor of the second inverter is a second pFET, further comprising a third gate terminal and a third drain terminal;
the second inverter further comprises a second pull-down nFET comprising a fourth drain terminal connected to the third drain terminal of the second pFET of the second inverter, comprising a fourth gate terminal, and comprising a fourth source terminal connected to the ground rail; and
wherein the first and second gates of the first pFET and the first nFET, respectively, of the first inverter are connected to the third drain of the second pFET of the second inverter, and the third and fourth gates of the second pFET and the second nFET, respectively, of the second inverter are connected to the first drain of the first pFET of the first inverter.
9. A system comprising:
a first die comprising a functional unit;
a second die comprising a processor, the second die distinct from the first die, the second die comprising:
a memory cell, the cell comprising:
a first inverter comprising a first pull-up transistor comprising a first body terminal and a first source terminal; and
a second inverter comprising a second pull-up transistor comprising a second body terminal and a second source terminal, wherein the first and second inverters are cross-coupled to each other;
a power rail coupled to the first and second source terminals, the power rail having a voltage Vcc; and
a bias voltage generator coupled to the first and second body terminals, the bias voltage generator having a voltage Vb, wherein Vb<Vcc.
10. The system as set forth in claim 9 , the second die further comprising:
a switch coupling the voltage Vb of the bias voltage generator to the first and second body terminals during a read operation on the memory cell.
11. The system as set forth in claim 10 , the second die further comprising a ground rail having a voltage Vss, where Vss<Vb, wherein
the first pull-up transistor of the first inverter is a first pFET, further comprising a first gate terminal and a first drain terminal;
the first inverter further comprises a first pull-down NFET comprising a second drain terminal connected to the first drain terminal of the first pFET of the first inverter, comprising a second gate terminal, and comprising a second source terminal connected to the ground rail;
the second pull-up transistor of the second inverter is a second pFET, further comprising a third gate terminal and a third drain terminal;
the second inverter further comprises a second pull-down nFET comprising a fourth drain terminal connected to the third drain terminal of the second pFET of the second inverter, the second pull-down nFET comprising a fourth gate terminal, and comprising a fourth source terminal connected to the ground rail; and
wherein the first and second gates of the first pFET and the first nFET, respectively of the first inverter are connected to the third drain of the second pFET of the second inverter, and the third and fourth gates of the second pFET and the second nFET, respectively of the second inverter are connected to the first drain of the first pFET of the first inverter.
12. The system as set forth in claim 9 , the second die further comprising a ground rail to provide a voltage Vss, where Vss<Vb, wherein
the first pull-up transistor of the first inverter is a first pFET, further comprising a first gate terminal and a first drain terminal;
the first inverter further comprises a first pull-down NFET comprising a second drain terminal connected to the first drain terminal of the first pFET of the first inverter, the first pull-down NFET comprising a second gate terminal, and comprising a second source terminal connected to the ground rail;
the second pull-up transistor of the second inverter is a second pFET, further comprising a third gate terminal and a third drain terminal;
the second inverter further comprises a second pull-down NFET comprising a fourth drain terminal connected to the third drain terminal of the second pFET of the second inverter, comprising a fourth gate terminal, and comprising a fourth source terminal connected to the ground rail; and
wherein the first and second gates of the first pFET and the first nFET, respectively, of the first inverter are connected to the third drain of the second pFET of the second inverter, and the third and fourth gates of the second pFET and the second nFET, respectively, of the second inverter are connected to the first drain of the first pFET of the first inverter.