Distribution of tasks among asymmetric processing elements

1. A system comprising:

a plurality of cores;

a memory interface circuit to communicatively couple the plurality of cores to system memory;

a plurality of execution resources of the plurality of cores to process a plurality of threads;

a cache to store instructions or data to be shared by the plurality of execution resources;

a first set of the plurality of execution resources to process a first set of one or more threads and a second set of the plurality of execution resources to process a second set of one or more threads, the first set of the plurality of execution resources having lower performance and consuming less power than the second set of the plurality of execution resources;

monitoring circuitry to detect an activity level and temperature associated with the plurality of execution resources;

a power controller to scale frequency and voltage of the plurality of execution resources in accordance with specified constraints; and

a thread management circuit to save a state of the first set of the plurality of execution resources, and then migrate a first thread and the state from the first set to the second set of the plurality of execution resources when the activity level rises above or the temperature falls below predetermined thresholds, the power controller to subsequently reduce a voltage and frequency of the first set of the plurality of execution resources.

2. The system as in claim 1 wherein the monitoring circuitry includes performance counters to detect the activity level.

3. The system as in claim 1 , wherein the thread management circuit is to migrate the first thread from the first set of the plurality of execution resources having lower performance and consuming less power than the second set of the plurality of execution resources in order to improve execution performance of the first thread, albeit at a cost of increased overall processor power consumption and temperature.

4. The system as in claim 1 further comprising:

a chipset interconnect to communicatively couple at least one of the plurality of cores to a chipset.

5. The system as in claim 1 further comprising:

an interconnect to communicatively couple at least one of the plurality of cores to a graphics core.

6. The system as in claim 1 further comprising:

an interconnect to communicatively couple at least one of the plurality of cores to a communication device.

7. The system as in claim 1 further comprising:

an interconnect to communicatively couple at least one of the plurality of cores to a storage device.

8. A method comprising:

processing a plurality of threads on a plurality of execution resources;

communicatively coupling the execution resources to a system memory;

storing instructions or data to be shared by the plurality of execution resources in a cache;

assigning a first set of the plurality of execution resources to process a first set of one or more threads;

assigning a second set of the plurality of execution resources to process a second set of one or more threads;

detecting an activity level and temperature associated with the plurality of execution resources;

scaling frequency and voltage of the plurality of execution resources in accordance with specified constraints;

saving a state of the first set of the plurality of execution resources, and

migrating a first thread and the state from the first set to the second set of the plurality of execution resources when the activity level rises above or the temperature falls below predetermined thresholds, and subsequently reducing a voltage and frequency of the first set of the plurality of execution resources.

9. The method as in claim 8 wherein detecting an activity level comprises reading a value from one or more performance counters.

10. The method as in claim 8 , wherein the specified constraints comprise one or more power constraints.

11. The method as in claim 8 , the first thread is migrated from the first set of the plurality of execution resources to the second set of the plurality of execution resources to improve execution performance of one or more of the plurality of threads.

12. An apparatus comprising:

means for processing a plurality of threads on a plurality of execution resources;

means for communicatively coupling the execution resources to a system memory;

means for storing instructions or data to be shared by the plurality of execution resources in a cache;

means for assigning a first set of the plurality of execution resources to process a first set of one or more threads;

means for assigning a second set of the plurality of execution resources to process a second set of one or more threads;

means for detecting an activity level and temperature associated with the plurality of execution resources;

means for scaling frequency and voltage of the plurality of execution resources in accordance with specified constraints;

means for saving a state of the first set of the plurality of execution resources, and

means for migrating a first thread and the state from the first set to the second set of the plurality of execution resources when the activity level rises above or the temperature falls below predetermined thresholds, the means for scaling frequency and voltage subsequently reducing a voltage and frequency of the first set of the plurality of execution resources.

13. The apparatus as in claim 12 wherein the means for detecting includes performance counters to detect the activity level.

14. The apparatus as in claim 12 , wherein the specified constraints comprise one or more power constraints.

15. The apparatus as in claim 12 wherein the means for migrating comprises migrating the first thread from the first set of the plurality of execution resources to the second set of the plurality of execution resources to improve execution performance of one or more of the plurality of threads.