IP Library Granted Patent US 7,554,975
Granted Patent B2
US 7,554,975 · App. 11/171,858 · Granted Jun 30, 2009

Protocol agnostic switching

Assignee: Intel Corporation
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,554,975
App. No.
11/171,858
Granted
Jun 30, 2009
Kind
B2
Abstract

In one embodiment, an apparatus comprises a switch fabric, an adaptation processor to append a length field to a received packet, and a switch fabric to use information in the length field to switch variable-sized packets.

Claims (46)

1. A computer-based apparatus for packet adaptation, comprising:

a switch fabric;

an adaptation processor to append a length field to a received packet;

a framing/byte-interleaving module to interleave the packet into a timeslot in a framing structure; and

a switch fabric to use information in the length field to switch variable-sized packets.

2. The apparatus of claim 1 , wherein the adaptation processor assigns a flow identifier to the received packet.

3. The apparatus of claim 2 , wherein:

the switch fabric includes a flow identifier table; and

the flow identifier table includes a pointer to a memory location associated with the switch fabric for the received packet.

4. The apparatus of claim 3 , wherein the switch fabric writes the memory location to an output queue associated with an output port.

5. The apparatus of claim 1 , wherein the adaptation processor is coupled to the switch fabric via a request-less interface.

6. The apparatus of claim 1 , wherein the adaptation processor comprises a flow manager module to assign a priority to the received packet.

7. A computer-based method for packet adaptation, comprising:

receiving a packet into a processor;

appending a length field to the packet;

appending a flow identifier to the packet;

byte-interleaving the packet into a timeslot in a framing structure' and

transmitting the packet to a switch fabric.

8. The method of claim 7 , further comprising:

receiving the packet in the switch fabric; and

using the flow id entifier to select a location in memory to store the packet.

9. The method of claim 8 , further comprising writing the packet to the memory location.

10. The method of claim 9 , further comprising writing the memory location to an output port associated with the switch fabric.

11. The method of claim 10 , further comprising switching the packet to the output port.

12. The method of claim 7 , wherein the length field identifies the length of the payload section of the data packet.

13. A computer-based method of packet adaptation, comprising:

receiving a packet into an adaptation processor;

retrieving a flow identifier from the packet;

selecting an output port using the flow identifier; and

mapping the packet to the output port; and

byte-interleaving the packet into a timeslot in a framing structure.

14. The method of claim 13 , further comprising performing an error check operation on the received packet.

15. The method of claim 13 , further comprising transmitting the packet.

16. A computer-based system for packet adaptation, comprising:

a first line card;

a backplane interface;

a second line card communicatively coupled to the first line card via the backplane interface and comprising a processor capable to append a length field to a received packet;

a framing/byte-interleaving module to interleave the packet into a timeslot in a framing structure;

a switch fabric to use information in the length field to switch variable-sized packets.

17. The system of claim 16 , wherein the backplane interface operates using a request-less communication protocol.

18. The system of claim 16 , wherein the second line card further comprises an adaptation processor assigns a flow identifier to the received packet.

19. The apparatus of claim 16 , wherein:

the switch fabric includes a flow identifier table; and

the flow identifier table includes a pointer to a memory location associated with the switch fabric for the received packet.

20. The apparatus of claim 16 , wherein the switch fabric includes a queue manager to manage a memory module in the switch fabric.

21. The apparatus of claim 20 , wherein the queue manager regulates traffic flow through the switch fabric.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2022
From: INTEL CORPORATION
To: TAHOE RESEARCH, LTD.
Reel/Frame 061175/0176 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 30, 2005
From: SMITH, ALEXANDER A.
To: INTEL CORPORATION
Reel/Frame 016728/0328 →
Continuity (1)
Related Publication 20070002854A1 · Jan 4, 2007