OPTIMIZING POWER USAGE BY FACTORING PROCESSOR ARCHITECTURAL EVENTS TO PMU
A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.
1 . A system comprising:
a plurality of processors;
a first interconnect to couple two or more of the plurality of processors;
a second interconnect to couple one or more of the plurality of processors to one or more other system components; and
a system memory coupled to one or more of the processors;
at least one of the processors comprising:
a plurality of last level cache (LLC) regions;
a plurality of cores coupled to one or more of the LLC regions, wherein a core of the plurality of cores comprises:
a plurality of thermal sensors to collect thermal data for the core, and
a plurality of performance counters to count architectural events within the core,
at least one counter to count completed instructions; and
a power management unit to manage power usage on a per core basis based on at least one of available power, thermal readings from the plurality of thermal sensors and/or architectural events counted by the performance counters, and to adjust a frequency of the core and to set a turbo mode based on the at least one available power.
2 . The system as in claim 1 wherein the plurality of LLC regions comprise at least four LLC regions.
3 . The system as in claim 1 wherein the plurality of cores comprise at least eight cores.
4 . The system as in claim 1 further comprising:
an accelerator device coupled to one or more of the processors over the first, the second, or a third interconnect.
5 . The system as in claim 1 wherein the system memory comprises a dynamic random access memory.
6 . The system as in claim 1 further comprising:
at least one communication device coupled to one or more of the plurality of processors.
7 . The system as in claim 1 further comprising:
at least one storage device coupled to one or more of the plurality of processors.
8 . The system as in claim 1 further comprising:
a graphics accelerator coupled to one or more of the plurality of processors.
9 . The system as in claim 8 further comprising:
a graphics interface to couple the graphics accelerator to the one or more of the plurality of processors; and
a display coupled to the graphics accelerator through the graphics interface.
10 . The system as in claim 7 further comprising:
a signal converter that translates a digital representation of an image stored in a storage device into display signals that are interpreted and displayed by the display.
12 . The system as in claim 9 further comprising a video memory usable by the graphics accelerator.
13 . The system as in claim 1 further comprising:
a user input device coupled to one or more of the plurality of processors over the second interconnect or a third interconnect.
14 . The system as in claim 1 further comprising:
an audio device coupled to one or more of the plurality of processors.