IP Library Granted Patent US 10,964,677
Granted Patent B2
US 10,964,677 · App. 15/845,492 · Granted Mar 30, 2021

Electronic packages with stacked sitffeners and methods of assembling same

Inventors: Jenny Shio Yin Ong (Bayan Lepas, MY); Bok Eng Cheah (Bukit Gambir, MY); Jackson Chung Peng Kong (Tanjung Tokong, MY); Seok Ling Lim (Kulim, MY); Kooi Chi Ooi (Glugor, MY)
Assignee: Intel Corporation
H01L25/16H01L21/4853H01L21/4875H01L23/13H01L23/16H01L23/36H01L23/3675H01L23/492H01L23/50H01L23/5389H01L23/562H01L24/16H01L24/32H01L24/73H01L23/49816H01L2224/16146H01L2224/16227H01L2224/16235H01L2224/17181H01L2224/3213H01L2224/32155H01L2224/32195H01L2224/73203H01L2924/1432H01L2924/19041H01L2924/19105H05K1/181H05K2201/10734
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Quick Facts
Patent No.
US 10,964,677
App. No.
15/845,492
Granted
Mar 30, 2021
Kind
B2
Abstract

A semiconductor package apparatus includes a passive device that is embedded in a bottom package stiffener, and a top stiffener is stacked above the bottom package stiffener. Electrical connection through the passive device is accomplished through the stiffeners to a semiconductor die that is seated upon an infield region of the semiconductor package substrate.

Claims (30)

1. A semiconductor package apparatus, comprising:

a semiconductor package substrate including a die side and land side;

a metal package stiffener coupled to the die side by an electrically conductive adhesive;

a plurality of capacitors, separate from the metal packager stiffener, and disposed in a plurality of recesses in the metal package stiffener, wherein each capacitor of the plurality of capacitors is electrically coupled to the metal package stiffener by a first contact; and

a plate stiffener electrically coupled to the plurality of capacitors by a second contact, wherein the plate stiffener is stacked above the metal package stiffener.

2. The semiconductor package apparatus of claim 1 , further including a semiconductive die disposed above the die side, Wherein the semiconductive die is electrically coupled to the plurality of capacitors through the semiconductor package substrate and also to the plate stiffener by a through-silicon via of the semiconductive die.

3. The semiconductor package apparatus of claim 1 , further including a semiconductive die disposed above the die side, wherein the semiconductive die is electrically coupled to the plurality of capacitors through the semiconductor package substrate and also to the plate stiffener.

4. The semiconductor package apparatus of claim 3 , wherein at least one of the plurality of capacitors is a first passive device, wherein the metal package stiffener is a first package stiffener, further including:

a subsequent package stiffener spaced apart from first package stiffener, the subsequent package stiffener including a subsequent recess in the subsequent package stiffener, wherein the subsequent package stiffener is adhered to the die side by an electrically conductive adhesive;

a subsequent passive device seated in the subsequent recess, wherein the subsequent passive device is electrically coupled to the subsequent package stiffener by a bottom contact, and wherein the plate stiffener is stacked above the subsequent package stiffener.

5. The semiconductor package apparatus of claim 4 , wherein the first package stiffener is configured for a first electrical potential, and wherein the subsequent package stiffener is configured for a subsequent electrical potential that is different from the first electrical potential.

6. The semiconductor package apparatus of claim 4 , wherein the first package stiffener exhibits a left-hand form factor, and wherein the subsequent package stiffener exhibits a right-hand form factor, further including a third package stiffener disposed on the die side between the first package stiffener and the subsequent package stiffener.

7. The semiconductor package apparatus of claim 1 wherein the package stiffener is one of a plurality of package stiffeners that form an infield upon the die side, and wherein the plate stiffener is stacked upon the plurality of package stiffeners, wherein each package stiffener includes at least one recess that is occupied by at least one passive device each.

8. The semiconductor package apparatus of claim 7 , wherein each of the plurality of package stiffeners includes at least two passive devices disposed within at least one recess.

9. The semiconductor package apparatus of claim 1 wherein the package stiffener is one of six package stiffeners that form an infield upon the die side, and wherein the plate stiffener is stacked upon the six package stiffeners, wherein each package stiffener includes at least one recess that is occupied by at least one passive device each.

10. The semiconductor package apparatus of claim 9 , wherein each of the six package stiffeners includes at least two passive devices disposed within at least one recess.

11. The semiconductor package apparatus of claim 1 , further including:

a first semiconductive die disposed upon the die side; and

a subsequent semiconductive die disposed above the first semiconductive die, wherein the subsequent semiconductive die is electrically coupled to the at least one of the plurality of capacitors through the semiconductor package substrate and also to the plate stiffener.

12. The semiconductor package apparatus of claim 1 , wherein the at least one of the plurality of capacitors is a decouple capacitor.

13. A semiconductor package apparatus, comprising:

a semiconductor package substrate including a die side and land side, and wherein the apparatus occupies a z-height;

a metal package stiffener coupled to the die side by an electrically conductive adhesive;

a plurality of capacitors, separate from the metal packager stiffener, and disposed in a plurality of recesses in the metal package stiffener, wherein each capacitor of the plurality of capacitors is electrically coupled to the metal package stiffener by a first contact, and wherein each of the plurality of capacitors occupies at least some of the same z-height; and

a plate stiffener electrically coupled to the plurality of capacitors by a second contact, wherein the plate stiffener is stacked above the metal package stiffener.

14. The semiconductor package apparatus of claim 13 , further including a semiconductive die disposed above the die side, wherein the semiconductive die is electrically coupled to the plurality of capacitors through the semiconductor package substrate and also to the plate stiffener by a through-silicon via of the semiconductive die.

15. The semiconductor package apparatus of claim 13 , further including a semiconductive die disposed above the die side, wherein the semiconductive die is electrically coupled to the plurality of capacitors through the semiconductor package substrate and also to the plate stiffener.

16. The semiconductor package apparatus of claim 15 , wherein at least one of the plurality of capacitors is a first passive device, wherein the metal package stiffener is a first package stiffener, further including:

a subsequent package stiffener spaced apart from first package stiffener, the subsequent package stiffener including a subsequent recess in the subsequent package stiffener, wherein the subsequent package stiffener is adhered to the die side by an electrically conductive adhesive;

a subsequent passive device seated in the subsequent recess, wherein the subsequent passive device is electrically coupled to the subsequent package stiffener by a bottom contact, and wherein the plate stiffener is stacked above the subsequent package stiffener.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2022
From: INTEL CORPORATION
To: TAHOE RESEARCH, LTD.
Reel/Frame 061175/0176 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 9, 2018
From: ONG, JENNY SHIO YIN; CHEAH, BOK ENG; KONG, JACKSON CHUNG PENG; LIM, SEOK LING; OOI, KOOI CHI
To: INTEL CORPORATION
Reel/Frame 045162/0190 →