High voltage field effect transistors
Transistors suitable for high voltage and high frequency operation are disclosed. A nanowire is disposed vertically or horizontally on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first semiconductor material, a source region electrically coupled with a first end of the channel region, a drain region electrically coupled with a second end of the channel region, and an extrinsic drain region disposed between the channel region and drain region. The extrinsic drain region has a wider bandgap than that of the first semiconductor. A gate stack including a gate conductor and a gate insulator coaxially wraps completely around the channel region, drain and source contacts similarly coaxially wrap completely around the drain and source regions.
1. A vertical transistor, comprising:
a cylindrical source region on and in direct contact with an uppermost surface of a substrate, the cylindrical source region having a center with an axis orthogonal to the uppermost surface of the substrate;
a cylindrical channel region above the cylindrical source region, the cylindrical channel region having a center co-axial with the axis;
a cylindrical extrinsic drain region above the cylindrical channel region, the cylindrical extrinsic drain region having a center co-axial with the axis;
a cylindrical drain region above the cylindrical extrinsic drain region, the cylindrical drain region having a center co-axial with the axis;
a gate stack comprising a gate insulator and a gate conductor coaxially wrapped completely around the cylindrical channel region;
a source contact coaxially wrapped completely around the cylindrical source region, the source contact in contact with the uppermost surface of the substrate; and
a drain contact coaxially wrapped completely around at least a portion of the cylindrical drain region.
2. The transistor of claim 1 , wherein the cylindrical extrinsic drain region has a band gap greater than a band gap of the cylindrical channel region.
3. The transistor of claim 1 , wherein the source contact is spaced apart from the cylindrical channel region by a first length, and wherein the drain contact is spaced apart from the cylindrical channel region by a second length greater than the first length.
4. The transistor of claim 1 , wherein the cylindrical drain region, the cylindrical channel region, and the cylindrical source region comprise a first semiconductor material, and the cylindrical extrinsic drain region comprises a second semiconductor material different than the first semiconductor material.
5. The transistor of claim 4 , wherein the first semiconductor material is InN and the second semiconductor material is GaN.
6. The transistor of claim 4 , wherein the first semiconductor material is GaAs and the second semiconductor material is AlGaAs.
7. The transistor of claim 4 , wherein the first semiconductor material is InAs and the second semiconductor material is InAlAs.
8. The transistor of claim 4 , wherein the first semiconductor material is Ge and the second semiconductor material is Si.
9. A vertical transistor, comprising:
a cylindrical drain region on and in direct contact with an uppermost surface of a substrate, the cylindrical drain region having a center with an axis orthogonal to the uppermost surface of the substrate;
a cylindrical extrinsic drain region above the cylindrical drain region, the cylindrical extrinsic drain region having a center co-axial with the axis;
a cylindrical channel region above the cylindrical extrinsic drain region, the cylindrical channel region having a center co-axial with the axis;
a cylindrical source region above the cylindrical channel region, the cylindrical source region having a center co-axial with the axis;
a gate stack comprising a gate insulator and a gate conductor coaxially wrapped completely around the cylindrical channel region;
a drain contact coaxially wrapped completely around the cylindrical drain region, the drain contact in contact with the uppermost surface of the substrate; and
a source contact coaxially wrapped completely around at least a portion of the cylindrical source region.
10. The transistor of claim 9 , wherein the cylindrical extrinsic drain region has a band gap greater than a band gap of the cylindrical channel region.
11. The transistor of claim 9 , wherein the source contact is spaced apart from the cylindrical channel region by a first length, and wherein the drain contact is spaced apart from the cylindrical channel region by a second length greater than the first length.
12. The transistor of claim 9 , wherein the cylindrical drain region, the cylindrical channel region, and the cylindrical source region comprise a first semiconductor material, and the cylindrical extrinsic drain region comprises a second semiconductor material different than the first semiconductor material.
13. The transistor of claim 12 , wherein the first semiconductor material is InN and the second semiconductor material is GaN.
14. The transistor of claim 12 , wherein the first semiconductor material is GaAs and the second semiconductor material is AlGaAs.
15. The transistor of claim 12 , wherein the first semiconductor material is InAs and the second semiconductor material is InAlAs.
16. The transistor of claim 12 , wherein the first semiconductor material is Ge and the second semiconductor material is Si.
17. A method of fabricating a vertical transistor, the method comprising:
epitaxially growing a cylindrical first source/drain region directly on an uppermost surface of a substrate, the cylindrical first source/drain region having a center with an axis orthogonal to the uppermost surface of the substrate;
forming a first source/drain contact coaxially wrapped completely around the cylindrical first source/drain region, the first source/drain contact in contact with the uppermost surface of the substrate;
epitaxially growing a cylindrical channel region above the cylindrical first source/drain region, the cylindrical channel region having a center co-axial with the axis;
forming a gate stack comprising a gate insulator and a gate conductor coaxially wrapped completely around the cylindrical channel region;
epitaxially growing a cylindrical second source/drain region above the cylindrical channel region, the cylindrical second source/drain region having a center co-axial with the axis; and
forming a second source/drain contact coaxially wrapped completely around at least a portion of the cylindrical second source/drain region; and
epitaxially growing a cylindrical extrinsic drain region between the cylindrical first source/drain region and the cylindrical channel region or between the cylindrical second source/drain region and the cylindrical channel region, the cylindrical extrinsic drain region having a center co-axial with the axis.
18. The method of claim 17 , wherein the cylindrical extrinsic drain region has a band gap greater than a band gap of the cylindrical channel region.
19. The method of claim 17 , wherein the first source/drain contact is spaced apart from the cylindrical channel region by a first length, and wherein the second source/drain contact is spaced apart from the cylindrical channel region by a second length greater than the first length.
20. The method of claim 17 , wherein the second source/drain contact is spaced apart from the cylindrical channel region by a first length, and wherein the first source/drain contact is spaced apart from the cylindrical channel region by a second length greater than the first length.
21. The method of claim 17 , wherein the cylindrical first source/drain region, the cylindrical channel region, and the cylindrical second source/drain region comprise a first semiconductor material, and the cylindrical extrinsic drain region comprises a second semiconductor material different than the first semiconductor material.
22. The method of claim 21 , wherein the first semiconductor material is InN and the second semiconductor material is GaN.
23. The method of claim 21 , wherein the first semiconductor material is GaAs and the second semiconductor material is AlGaAs.
24. The method of claim 21 , wherein the first semiconductor material is InAs and the second semiconductor material is InAlAs.
25. The method of claim 21 , wherein the first semiconductor material is Ge and the second semiconductor material is Si.