High voltage field effect transistors
View Patent ↗Transistors suitable for high voltage and high frequency operation are disclosed. A nanowire is disposed vertically or horizontally on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first semiconductor material, a source region electrically coupled with a first end of the channel region, a drain region electrically coupled with a second end of the channel region, and an extrinsic drain region disposed between the channel region and drain region. The extrinsic drain region has a wider bandgap than that of the first semiconductor. A gate stack including a gate conductor and a gate insulator coaxially wraps completely around the channel region, drain and source contacts similarly coaxially wrap completely around the drain and source regions.
1. A method of forming a high voltage transistor on a substrate, the method comprising:
epitaxially growing a stack of semiconductor materials on the substrate, the stack comprising at least a first semiconductor material and a second semiconductor material having a larger bandgap than a bandgap of the first semiconductor material;
etching the stack to define a nanowire;
forming a drain contact coaxially wrapping completely around the first semiconductor material along a longitudinal drain length of the nanowire;
forming a source contact coaxially wrapping completely around the first semiconductor material along a longitudinal source length of the nanowire;
forming a gate conductor coaxially wrapping completely around the first semiconductor material along a longitudinal channel length of the nanowire, wherein the gate conductor is spaced apart from the drain contact by an extrinsic drain region comprising the second semiconductor material.
2. The method of claim 1 , wherein etching the stack further comprises etching a longitudinal length of the nanowire, and wherein forming the gate conductor, drain contact, and source contact, further comprises:
removing the second semiconductor material selectively relative to the first semiconductor material to form a gap between the first semiconductor material and the substrate along each of the longitudinal channel, source, and drain lengths;
wherein forming gate conductor further comprises backfilling the gap with the gate insulator and gate conductor along the longitudinal channel length; and
wherein forming the drain contact and source contact further comprises backfilling the gap with an ohmic metal along the longitudinal drain and source lengths.
3. The method of claim 1 , further comprising removing the first semiconductor material selectively relative to the second semiconductor material to form a gap over the second semiconductor material and epitaxially regrowing a crystalline semiconductor material in the gap that has a larger bandgap than the bandgap of the first semiconductor material.
4. The method of claim 1 , further comprising:
thermal annealing to intermix the first and second semiconductor materials remaining within the extrinsic drain region.
5. The method of claim 1 , further comprising:
selectively depositing a diffusive element selected from the group consisting of: Al, Ga, and Zn, on the first semiconductor material within the extrinsic drain region; and
thermal annealing to intermix the first semiconductor material with the diffusive element.
6. The method of claim 1 , wherein epitaxially growing the stack of semiconductor materials further comprises:
epitaxially growing on the substrate, a first layer consisting essentially of the first semiconductor material and a high level of n-type dopant;
epitaxially growing, on the first layer, a second layer consisting essentially of the second semiconductor material and a low level of n-type dopant; and
epitaxially growing, on the second layer, a third layer consisting essentially of the first semiconductor material, undoped; and
epitaxially growing, on the third layer, a fourth layer consisting essentially of the first semiconductor material and a high level of source region dopant.
7. The method of claim 6 , wherein the source region dopant comprises a p-type dopant to form a tunnel junction.
8. The method of claim 6 , wherein etching the stack further comprises etching through each of the first, second, third and fourth layers to define the nanowire, and wherein forming a drain contact further comprises:
depositing a drain contact material on the nanowire; and
anisotropically etching the drain contact material to form a drain contact material spacer having a height approximately equal to a thickness of the first layer.
9. The method of claim 8 , wherein forming the forming a gate conductor further comprises:
depositing a dielectric material on the nanowire and on the drain contact material;
anisotropically etching the dielectric material to form a first dielectric spacer surrounding the nanowire, the first dielectric spacer disposed on the drain contact material; the first dielectric spacer laterally adjacent to the second layer and having a height approximately equal to a thickness of the second layer;
depositing the gate insulator on the nanowire and on the first dielectric spacer;
depositing the gate conductor on the gate insulator;
anisotropically etching the gate conductor to a height approximately equal to the third layer wherein the gate conductor is laterally adjacent to the third layer; and
removing the gate insulator not protected by the gate conductor.
10. The method of claim 9 , wherein forming the source contact further comprises:
depositing a dielectric material on the nanowire and on the gate conductor;
anisotropically etching the dielectric material to form a second dielectric spacer surrounding the nanowire and disposed on the gate conductor, the second dielectric material spacer laterally adjacent to the fourth layer and having a height less than a thickness of the fourth layer; and
depositing a source contact material on the nanowire and on the second dielectric spacer.