IP Library Granted Patent US 7,274,250
Granted Patent B2
US 7,274,250 · App. 11/170,559 · Granted Sep 25, 2007

Low-voltage, buffered bandgap reference with selectable output voltage

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Quick Facts
Patent No.
US 7,274,250
App. No.
11/170,559
Granted
Sep 25, 2007
Kind
B2
Abstract

A temperature-independent voltage reference containing two independent bias circuits powered by the reference voltage, each bias circuit containing components with an exponential dependence of current on voltage and one containing a resistive impedance, and further including voltage dividers and an active component.

Claims (61)

1. An apparatus comprising:

a first bias circuit to bias a first component with an exponential dependency of current on voltage (“exponential I(V) characteristic”) at a first point of its range;

a second, independent bias circuit to bias a second component with an exponential I(V) characteristic at a second point of its range, the first point being different than the second point;

a resistive impedance in series with the second component;

a first voltage divider to produce a first voltage proportional to a voltage across the first component;

a second voltage divider to produce a second voltage proportional to a sum of a voltage across the second component and a voltage across the resistive impedance; and

an active component to compare the first voltage and the second voltage and to produce a reference voltage; wherein in operation a current through each voltage divider is greater than zero, and

the bias circuits are powered by the reference voltage.

2. The apparatus of claim 1 wherein the first and second components are diodes.

3. The apparatus of claim 1 wherein the first and second components are bipolar transistors.

4. The apparatus of claim 1 wherein the first bias circuit comprises a first resistor in series with the first component and the second bias circuit comprises a second resistor in series with the second component and the resistive impedance.

5. The apparatus of claim 4 wherein the first voltage divider comprises a first divider resistor in series with a second divider resistor; and the second voltage divider comprises a third divider resistor in series with a fourth divider resistor.

6. The apparatus of claim 5 wherein:

α is a ratio between a sum of the first divider resistor and the second divider resistor; and a sum of the first resistor, the first divider resistor and the second divider resistor;

β is a ratio between the second divider resistor and a sum of the first divider resistor and the second divider resistor;

γ is a ratio between a sum of the third divider resistor and the fourth divider resistor; and a sum of the second resistor, the third divider resistor and the fourth divider resistor; and

δ is a ratio between the third divider resistor and a sum of the third divider resistor and the fourth divider resistor; where

0<α=γ<1 and 0<β=δ≦1.

7. The apparatus of claim 5 wherein:

α is a ratio between a sum of the first divider resistor and the second divider resistor; and a sum of the first resistor, the first divider resistor and the second divider resistor;

β is a ratio between the second divider resistor and a sum of the first divider resistor and the second divider resistor;

γ is a ratio between a sum of the third divider resistor and the fourth divider resistor; and a sum of the second resistor, the third divider resistor and the fourth divider resistor; and

δ is a ratio between the third divider resistor and a sum of the third divider resistor and the fourth divider resistor; where

0<γ<α<1; and β=δ*γ/α.

8. The apparatus of claim 1 wherein the reference voltage is not equal to a bandgap voltage.

9. The apparatus of claim 1 wherein the reference voltage is less than a bandgap voltage.

10. The apparatus of claim 1 wherein the reference voltage is greater than a bandgap voltage.

11. The apparatus of claim 5 wherein:

α is a ratio between a sum of the first divider resistor and the second divider resistor; and a sum of the first resistor, the first divider resistor and the second divider resistor;

γ is a ratio between a sum of the third divider resistor and the fourth divider resistor; and a sum of the second resistor, the third divider resistor and the fourth divider resistor;

R 2 is a Thevenin equivalent resistance of the second bias circuit and the second voltage divider;

R 3 is a resistance of the resistive impedance in series with the second component; and

K

is

1

α

+

R

2

R

3

*

(

1

α

-

1

γ

)

;

the reference voltage being substantially equal to a product of K and a bandgap voltage.

12. The apparatus of claim 1 wherein a maximum permissible voltage for the active component does not exceed a bandgap voltage.

13. The apparatus of claim 1 wherein:

a maximum permissible voltage for the active component exceeds a bandgap voltage; and

the reference voltage is less than the bandgap voltage.

14. The apparatus of claim 1 wherein the reference voltage is less than 1.2 volts.

15. The apparatus of claim 8 wherein the first component with an exponential I(V) characteristic is formed upon a silicon substrate.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2022
From: INTEL CORPORATION
To: TAHOE RESEARCH, LTD.
Reel/Frame 061175/0176 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 28, 2005
From: HAZUCHA, PETER; MOON, SUNG T.; SCHROM, GERHARD; PAILLET, FABRICE; KARNIK, TANAY; DE, VIVEK
To: INTEL CORPORATION
Reel/Frame 016746/0252 →