Logic chip including embedded magnetic tunnel junctions
An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-M RAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) that has an upper MTJ layer, a lower MTJ layer, and a tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. Other embodiments are described herein.
1. A magnetic random access memory structure, comprising:
a first material layer comprising tantalum; a second material layer on the first material layer, the second material layer comprising platinum and manganese;
a third material layer on the second material layer, the third material layer comprising cobalt and iron;
a fourth material layer on the third material layer, the fourth material layer comprising ruthenium;
a fifth material layer on the fourth material layer, the fifth material layer comprising cobalt, iron and boron, the fifth material layer having a first lateral width;
a tunnel barrier layer on the fifth material layer, the tunnel barrier layer comprising magnesium and oxygen;
a sixth material layer on the tunnel barrier layer, the sixth material layer comprising cobalt, iron and boron, the sixth material layer having an uppermost surface;
a seventh material layer above the sixth material layer, the seventh material layer comprising tantalum, and the seventh material layer having a second lateral width less than the first lateral width;
a spacer along sidewalls of the seventh material layer, the spacer having a bottommost surface above the uppermost surface of the sixth material layer.
2. The magnetic random access memory structure of claim 1 , wherein the first material layer has a thickness of 3 nanometers.
3. The magnetic random access memory structure of claim 1 , wherein the second material layer has a thickness of 20 nanometers.
4. The magnetic random access memory structure of claim 1 , wherein the third material layer has a thickness of 2.3 nanometers.
5. The magnetic random access memory structure of claim 1 , wherein the fourth material layer has a thickness of 0.8 nanometers.
6. The magnetic random access memory structure of claim 1 , wherein the fifth material layer has a thickness of 2.5 nanometers.
7. The magnetic random access memory structure of claim 1 , wherein the tunnel barrier layer has a thickness of 1.2 nanometers.
8. The magnetic random access memory structure of claim 1 , wherein the sixth material layer has a thickness of 2.5 nanometers.
9. The magnetic random access memory structure of claim 1 , wherein the seventh material layer has a thickness of 50 nanometers.
10. The magnetic random access memory structure of claim 1 , wherein the fifth and sixth material layers comprise Co 60 Fe 20 B 20 .
11. The magnetic random access memory structure of claim 1 , wherein the spacer comprises oxygen.
12. The magnetic random access memory structure of claim 11 , wherein the spacer comprises silicon oxide or silicon oxynitride.
13. A magnetic random access memory structure, comprising:
a first material layer comprising tantalum;
a second material layer on the first material layer, the second material layer comprising platinum and manganese;
a third material layer on the second material layer, the third material layer comprising cobalt and iron;
a fourth material layer on the third material layer, the fourth material layer comprising ruthenium;
a bottom magnetic tunnel junction layer on the fourth material layer, the bottom magnetic tunnel junction layer comprising cobalt, iron and boron, the bottom magnetic tunnel junction layer having a first lateral width;
a tunnel barrier layer on the bottom magnetic tunnel junction layer, the tunnel barrier layer comprising magnesium and oxygen;
a top magnetic tunnel junction layer on the tunnel barrier layer, the top magnetic tunnel junction layer comprising cobalt, iron and boron, the top magnetic tunnel junction layer having an uppermost surface;
a hardmask above the top magnetic tunnel junction layer, the hardmask comprising tantalum, and the hardmask having a second lateral width less than the first lateral width;
a spacer along sidewalls of the hardmask, the spacer having a bottommost surface above the uppermost surface of the top magnetic tunnel junction layer.
14. The magnetic random access memory structure of claim 13 , wherein the first material layer has a thickness of 3 nanometers, wherein the second material layer has a thickness of 20 nanometers, wherein the third material layer has a thickness of 2.3 nanometers, and wherein the fourth material layer has a thickness of 0.8 nanometers.
15. The magnetic random access memory structure of claim 13 , wherein the bottom magnetic tunnel junction layer has a thickness of 2.5 nanometers, wherein the tunnel barrier layer has a thickness of 1.2 nanometers, and wherein the top magnetic tunnel junction layer has a thickness of 2.5 nanometers.
16. The magnetic random access memory structure of claim 13 , wherein the hardmask has a thickness of 50 nanometers.
17. The magnetic random access memory structure of claim 13 , wherein the hardmask is a conductive hardmask.
18. The magnetic random access memory structure of claim 13 , wherein the bottom magnetic tunnel junction layer and the top magnetic tunnel junction layer comprise Co 60 Fe 20 B 20 .
19. The magnetic random access memory structure of claim 13 , wherein the spacer comprises oxygen.
20. The magnetic random access memory structure of claim 19 , wherein the spacer comprises silicon oxide or silicon oxynitride.