Reduced current requirements for DRAM self-refresh modes via staggered refresh operations of subsets of memory banks or rows
View Patent ↗Embodiments of the invention describe systems, methods, and apparatuses to reduce the instantaneous power necessary to execute a DRAM device initiated self-refresh. Embodiments of the invention describe a DRAM device enabled to stagger self-refreshes between a plurality of banks. Staggering self-refreshes between banks reduces the current required for a DRAM self-refresh, thus reducing the amount of current required by the DRAM device.
1. A system comprising:
a dynamic random access memory (DRAM) device to execute a self-refresh mode, the DRAM device including a plurality of banks, each bank to include a plurality of rows, the self-refresh mode to include a plurality of commands, each command to refresh rows of one of the banks;
a memory controller operatively coupled to the DRAM device; and
logic, operatively coupled to the DRAM device and the memory controller, to:
determine the number of banks included in the DRAM device,
determine characteristics of power supplied to the DRAM device, and
determine a plurality of subsets of banks or rows to be concurrently refreshed in the self-refresh mode, wherein determining the plurality of subsets to be concurrently refreshed is based, at least in part, on the characteristics of power supplied to the DRAM device;
the DRAM device to execute the self-refresh mode for each of the plurality of subsets in a staggered fashion.
2. The system of claim 1 , wherein each of the plurality of subsets includes half of the number of banks included in the DRAM device.
3. The system of claim 1 , wherein each of the plurality of subsets consists of one of the plurality of banks.
4. The system of claim 1 , the memory controller to transmit a signal to the DRAM device to enable the DRAM device to execute the self-refresh mode for each of the plurality of subsets in the staggered fashion.
5. The system of claim 1 , the logic included in a basic input/output system (BIOS).
6. The system of claim 1 , each command of the self-refresh mode to refresh a subset of rows of one of the banks
7. A method comprising:
determining the number of banks included in a DRAM device, the DRAM device to include a plurality of banks, each bank to include a plurality of rows;
determining characteristics of power supplied to the DRAM device;
determining a plurality of subsets of banks or rows to be concurrently refreshed in a self-refresh mode based, at least in part, on the characteristics of power supplied to the DRAM device, the self-refresh mode to include a plurality of commands, each command to refresh rows of one of the banks; and
executing the self-refresh mode for each of the plurality of subsets in a staggered fashion.
8. The method of claim 7 , wherein each of the plurality of subsets comprises half of the number of banks included in the DRAM device.
9. The method of claim 7 , wherein each of the plurality of subsets consists of one of the plurality of banks.
10. The method of claim 7 , further comprising:
receiving a signal at the DRAM device to enable the device to execute the self-refresh mode for each of the plurality of subsets in the staggered fashion.
11. The method of claim 7 , each command of the self-refresh mode to refresh a subset of rows of one of the banks.
12. An apparatus comprising:
a plurality of DRAM banks, each DRAM bank to include a plurality of rows;
a first logic, operatively coupled to the DRAM banks, to determine characteristics of power supplied to the apparatus; and
a second logic, operatively coupled to the DRAM banks and the first logic, to:
execute a self-refresh mode for the plurality of subsets of DRAM banks or rows in a staggered fashion, the self-refresh mode to include a plurality of commands, each command to refresh rows of one of the DRAM banks; and
determine the plurality of subsets to be refreshed based, at least in part, on the characteristics of power supplied to the apparatus.
13. The apparatus of claim 12 , wherein each of the plurality of subsets comprises half of the number of DRAM banks.
14. The apparatus of claim 12 , wherein each of the plurality of subsets consists of one of the plurality of DRAM banks.
15. The apparatus of claim 12 wherein the second logic to further:
receive a signal from a memory controller to enable the apparatus to execute the self-refresh mode for each of the plurality of subsets in the staggered fashion.
16. The apparatus of claim 12 , each command of the self-refresh mode to refresh a subset of rows of one of the DRAM banks.
17. The apparatus of claim 12 , wherein the characteristics of power supplied to the apparatus comprises at least one of an amount of the power supplied to the apparatus, a voltage requirement of the apparatus, or a current value of the power supplied to the apparatus.