Frequency multiplying delay-locked loop
View Patent ↗Frequency multiplying delay-locked loop techniques are described in which a plurality of phase shifted signals are generated utilizing a delay-locked loop circuit having a clock multiplication, the phase shifted signals having increased frequency relative to the incoming signal. The phase-shifted signals being generated by the delay-locked loop in order to position the clock to an optimal detection point of incoming data signals.
1. An apparatus comprising:
a multiplier portion to form a signal having increased frequency relative to an input clock signal from which the multiplier portion forms the signal having the increased frequency, wherein the multiplier portion includes a plurality of stages each of which is to produce a respective doubling of the frequency relative to the input clock signal; and
a delay-locked loop (DLL) portion to produce a plurality of phase shifted outputs from the signal having the increased frequency.
2. An apparatus as recited in claim 1 , wherein the plurality of phase shifted outputs have equal phase spacing one to another.
3. An apparatus as recited in claim 1 , wherein the delay-locked loop (DLL) portion operates at the increased frequency.
4. An apparatus as recited in claim 1 , wherein the delay-locked loop (DLL) portion has a plurality of delay cells arranged in series to produce the plurality of phase shifted outputs.
5. An apparatus as recited in claim 4 , wherein the number of delay cells in the delay-locked loop (DLL) portion is equal to the number of phase shifted outputs produced.
6. An apparatus as recited in claim 1 , wherein the increased frequency of the plurality of phase shifted output signals is increased four times relative to the input clock signal.
7. An apparatus as recited in claim 1 , wherein:
the multiplier portion is to provide a signal having double the frequency of the input clock signal to the delay-locked loop portion, and;
the delay-locked loop portion is to produce eight equally spaced phase shifted outputs from the signal provided by the multiplier portion.
8. An apparatus as recited in claim 7 , wherein the eight equally spaced phase shifted outputs are spaced 45 degrees apart.
9. An apparatus as recited in claim 1 , further comprising a control mechanism which provides voltage control shared by the multiplier portion and the delay-locked loop.
10. A method comprising:
receiving an input clock signal at a first integrated circuit of an electronic system;
forming from the input clock signal, a clock signal having increased frequency relative to input clock signal, wherein the forming occurs via a multiplier portion of the first integrated circuit having:
a plurality of delay cells to produce a delayed version of the input clock signal; and
a multiplier device to produce the signal having increased frequency from the input clock signal and the delayed version of the input clock signal; and
producing from the increased frequency clock signal a plurality of phase shifted outputs having equal phase spacing one to another.
11. A method as recited in claim 10 , wherein the plurality of phase shifted outputs each have the increased frequency relative to the input clock signal.
12. A method as recited in claim 10 , wherein the input clock signal is received via a component interconnect from a second integrated circuit of the electronic system.
13. A method as recited in claim 10 , wherein the plurality of phase shifted output signals are to control the timing of one or more operations of the first integrated circuit.
14. A method as recited in claim 10 , wherein the producing occurs via a delay-locked loop (DLL) portion having a plurality of delay cells to produce the plurality of phase shifted outputs.
15. A method as recited in claim 14 , wherein the delay-locked loop (DLL) portion operates at the increased frequency.
16. A method as recited in claim 10 , wherein the increased frequency is increased at least four times relative to the input clock signal.
17. A method as recited in claim 10 , wherein:
the forming occurs via a multiplier portion of the first integrated circuit having:
a plurality of delay cells to produce a delayed version of the input clock signal; and
a multiplier device to form the signal having increased frequency from the input clock signal and the delayed version of the input clock signal,
the producing occurs via a delay-locked loop (DLL) portion of the first integrated circuit having a plurality of delay cells arranged in series to produce the plurality of phase shifted outputs;
the multiplier portion is to provide a signal having double the frequency of the input clock signal to the delay-locked loop (DLL) portion, and
the delay-locked loop (DLL) portion is to produce eight equally spaced phase shifted outputs from the signal provided by the multiplier portion.
18. A system comprising:
a processor core having a dynamic random access memory (dram); and
a circuit to produce a plurality of phase shifted output clock signals from an input clock signal, the circuit having:
a multiplier portion to receive the input clock signal and form a signal having increased frequency relative to the input clock signal;
a delay-locked loop (DLL) portion to receive the signal formed by the multiplier portion and produce the plurality of phase shifted output clock signals having the increased frequency; and
a control mechanism which provides voltage control shared by the multiplier portion and the delay-locked loop.
19. A system as recited in claim 18 wherein the plurality of phase shifted output clock signals have equal phase spacing one to another.
20. A system as recited in claim 18 , wherein the increased frequency is increased at least three times relative to the input clock signal.
21. A system as recited in claim 16 , wherein
the multiplier portion is to double the frequency of the input clock signal, and;
the delay-locked loop (DLL) portion is to produce eight evenly spaced phase shifted output clock signals.
22. An apparatus comprising:
a multiplier portion to form a signal having increased frequency relative to an input clock signal from which the multiplier portion forms the signal having the increased frequency, wherein the multiplier portion includes:
a plurality of delay cells to produce a delayed version of the input clock signal; and
a multiplier device to form the signal having increased frequency from the input clock signal and the delayed version of the input clock signal; and
a delay-locked loop (DLL) portion to produce a plurality of phase shifted outputs from the signal having the increased frequency.
23. An apparatus as recited in claim 22 , wherein the multiplier device is to double the frequency of the input clock signal.
24. An apparatus comprising:
a multiplier portion to form a signal having increased frequency relative to a input clock signal from which the multiplier portion forms the signal having the increased frequency;
a delay-locked loop (DLL) portion to produce a plurality of phase shifted outputs from the signal having the increased frequency; and
a control mechanism which provides voltage control shared by the multiplier portion and the delay-locked loop.
25. A method comprising:
receiving an input clock signal at a first integrated circuit of an electronic system;
forming from the input clock signal, a clock signal having increased frequency relative to input clock signal, the forming occurs via a multiplier portion of the first integrated circuit having:
a plurality of delay cells to produce a delayed version of the input clock signal; and
a multiplier device to form the signal having increased frequency from the input clock signal and the delayed version of the input clock signal;
producing from the increased frequency clock signal a plurality of phase shifted outputs having equal phase spacing one to another, the producing occurs via a delay-locked loop (DLL) portion of the first integrated circuit having a plurality of delay cells arranged in series to produce the plurality of phase shifted outputs;
the multiplier portion is to provide a signal having double the frequency of the input clock signal to the delay-locked loop (DLL) portion, and
the delay-locked loop (DLL) portion is to produce eight equally spaced phase shifted outputs from the signal provided by the multiplier portion.