Method of forming a stacked device filler
View Patent ↗Numerous embodiments of a stacked device filler and a method of formation are disclosed. In one embodiment, a method of forming a stacked device filler comprises forming a material layer between two or more substrates of a stacked device, and causing a reaction in at least a portion of the material, wherein the reaction may comprise polymerization, and the material layer may be one or a combination of materials, such as nonconductive polymer materials, for example.
1. A stacked microelectronic device, comprising:
a first substrate;
a plurality of interconnect structures formed on at least a portion of the first substrate;
a layer of polymer foam formed on at least a portion of the first substrate adjacent to the interconnect structures, the polymer foam including polystyrene, polyester, polyurethane, or a combination thereof; and
a second substrate with a plurality of interconnect structures formed thereon, said first and second substrate interconnect structures configured such that at least a portion of the interconnect structures of said first and second substrate respectively are in physical contact.
2. The apparatus of claim 1 , wherein the apparatus comprises a stacked chipset.
3. The apparatus of claim 1 wherein the first and second substrates comprise integrated circuits.
4. The apparatus of claim 1 , wherein at least a portion of the interconnect structures comprise copper vias.
5. A stacked microelectronic device, comprising:
a first substrate;
a plurality of interconnect structures formed on at least a portion of the first substrate;
a filler formed on at least a portion of the first substrate adjacent to the interconnect structures, the filler including a combination of
a first material including diisocyanate monomers, a diisocyanate end-capped compliant oligomer, p-toluenesulfonyl semicarbazide, or a combination thereof, and
a second material including water, a hydroxyl end-capped oligomer, a carboxylic acid end-capped polymer, or a combination thereof; and
a second substrate with a plurality of interconnect structures formed thereon, the first and second substrate interconnect structures configured such that at least a portion of the interconnect structures of the first and second substrate respectively are in physical contact.
6. The apparatus of claim 5 , wherein the apparatus comprises a stacked chipset.
7. The apparatus of claim 5 , wherein the first and second substrates comprise integrated circuits.
8. The apparatus of claim 5 , wherein at least a portion of the interconnect structures comprise copper vias.