Embedding device in substrate cavity
View Patent ↗An embodiment of the present invention is a technique to reduce interconnect length between devices. A cavity is formed in a substrate having a substrate surface. The cavity has a depth. A first device having a device surface and a thickness is placed into the cavity. The thickness matches the depth such that the device surface is approximately planar with the substrate surface. The first device is attached to a second device via bumps on the second device.
1. A method comprising:
forming a cavity in a substrate having a substrate surface, the cavity having a depth;
placing a first device having a device surface and a thickness into the cavity, the thickness matching the depth such that the device surface is approximately planar with the substrate surface; and
attaching the first device to a second device via bumps on the second device; wherein attaching the first device to the second device comprises:
filling the cavity with a solder resist;
forming solder bumps on the substrate surface and on the solder resist; and
reflowing the bumps on the second device to the solder bumps.
2. The method of claim 1 wherein forming the cavity comprises:
depositing a metal layer on a substrate core.
3. The method of claim 2 wherein forming the cavity further comprising:
depositing a dielectric layer on the metal layer;
depositing a solder resist on the dielectric layer; and
routing the cavity to fit the first device.
4. The method of claim 3 wherein routing the cavity comprises:
drilling the solder resist and the dielectric layer using one of an etching process, a laser drilling, and a mechanical drilling bit.
5. The method of claim 2 wherein forming the cavity further comprises:
depositing a dielectric layer on the metal layer;
drilling the dielectric layer using a laser;
plating electroless metal on the drilled dielectric layer;
laminating a dry film resist (DFR) on the metal plated dielectric layer; and
patterning interconnect with electrolytic metal plating using a semi additive process (SAP).
6. The method of claim 5 wherein forming the cavity further comprises:
etching the DFR to expose the cavity.
7. The method of claim 1 wherein the first device is a memory device and the second device is a processor.