IP Library Granted Patent US 7,339,271
Granted Patent B2
US 7,339,271 · App. 10/861,657 · Granted Mar 4, 2008

Metal-metal oxide etch stop/barrier for integrated circuit interconnects

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,339,271
App. No.
10/861,657
Granted
Mar 4, 2008
Kind
B2
Abstract

Described is a method and apparatus for forming interconnects with a metal-metal oxide electromigration barrier and etch-stop. In one embodiment of the invention, the method includes depositing a metal layer on the top of a planarized interconnect layer, the interconnect layer having an interlayer dielectric (ILD) with a top that is planar with the top of an electrically conductive interconnect. In one embodiment of the invention, the method includes reacting the metal layer with the ILD to form a metal oxide layer on the top of the ILD. At the same time, the metal layer will not be significantly oxidized by the electrically conductive interconnect, thus forming a metal barrier on the electrically conductive interconnect to improve electromigration performance. The metal barrier and metal oxide layer together comprise a protective layer. A second ILD may be subsequently formed on the protective layer, and the protective layer may act an etch-stop during a subsequent etch of the second ILD.

Claims (35)

1. An apparatus, comprising:

a first ILD;

an interconnect within the first ILD, the interconnect having a top surface planarized to a top surface of the first ILD;

a protective layer on the top surface of the interconnect and on the top surface of the first ILD, the protective layer including a metal oxide portion covering the top surface of the first ILD and an electromigration barrier covering the top surface of the interconnect, wherein the metal oxide portion protrudes below a plane defined by the top surface of the interconnect; and

a second ILD on at least the metal oxide portion of the protective layer, wherein the second ILD is in direct contact with the protective layer.

2. The apparatus of claim 1 , wherein the protective layer is to act as an etch-stop during etching and cleaning of the second ILD.

3. The apparatus of claim 1 , wherein the electromigration barrier comprises a metal and is to improve electromigration of the interconnect.

4. The apparatus of claim 1 , wherein the first ILD portion comprises an oxide material.

5. The apparatus of claim 1 , wherein the first ILD portion comprises a material selected from the group consisting of SiO 2 , SiOF, and CDO.

6. The apparatus of claim 1 , wherein the electromigration barrier covering the interconnect comprises a material selected from the group consisting of cobalt, aluminum, tantalum, chromium, and titanium.

7. The apparatus of claim 1 , wherein the protective layer has a thickness between approximately 10 Å to 100 Å.

8. An apparatus, comprising:

a substrate;

an interconnect layer overlying the substrate, the interconnect layer including an electrically conductive interconnect having a top surface planarized to a top surface of a first ILD;

a protective layer on the interconnect layer, the protective layer including a metal oxide portion covering the first ILD and an electromigration barrier covering the interconnect, wherein the metal oxide portion protrudes below a plane defined by the top surface of the interconnect;

and

a second JLD on at least the metal oxide portion of the protective layer.

9. The apparatus of claim 8 , wherein the protective layer is to act as an etch-stop.

10. The apparatus of claim 8 , wherein the electromigration barrier comprises metal and is to improve electromigration of the interconnect.

11. The apparatus of claim 8 , wherein the first RD comprises an oxide material.

12. The apparatus of claim 8 , wherein the electromigration barrier covering the interconnect comprises a material that can react, on contact, with an oxide material to form metal oxide.

13. A semiconductor device comprising:

a first interconnect layer including a first ILD and an electrically conductive interconnect within the first ILD;

a protective layer on the first interconnect layer, the protective layer including a metal oxide layer covering the first ILD and an electromigration barrier covering the interconnect, wherein a bottom surface of the metal oxide layer protrudes below a plane defined by a top surface of the interconnect; and

a second interconnect layer including a second ILD and an unlanded via within the second ILD, the unlanded via electrically connected to the interconnect, wherein at least a first portion of the second ILD is in direct contact with the metal oxide layer and at least a second portion of the second ILD is in direct contact with the electromigration barrier.

14. The device of claim 13 , wherein the protective layer and the second ILD have different etching properties.

15. The device of claim 13 , wherein the protective layer has a thickness between approximately 10 Å to 100 Å.

16. The device of claim 13 , wherein the first ILD contains oxygen.

17. The device of claim 13 , wherein the electromigration barrier comprises a metal material that can react, on contact, with an oxide material to form metal oxide.

18. The device of claim 17 , wherein

the metal material comprises a material selected from the group consisting of cobalt, aluminum, tantalum, chromium, and titanium; and

the metal oxide layer comprises one of cobalt oxide, aluminum oxide, tantalum oxide, chromium oxide, or titanium oxide.

19. The device of claim 13 , further comprising:

a substrate beneath the first ILD; and

a conductor within the substrate electrically connected to the interconnect.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2022
From: INTEL CORPORATION
To: TAHOE RESEARCH, LTD.
Reel/Frame 061175/0176 →