Methods for patterning a semiconductor film
View Patent ↗A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.
1. A method of patterning a monocrystalline silicon film comprising:
forming a hard mask on a monocrystalline silicon film;
etching said monocrystalline silicon film in alignment with said hard mask to form a monocrystalline silicon structure with a top surface and a pair of laterally opposite sidewalls, said monocrystalline silicon structure covered with said hard mask; and
exposing, to etch away a portion of said monocrystalline silicon structure, said monocrystalline silicon structure covered with said hard mask to a wet chemical etchant comprising water and less than 1% by volume NH 4 OH, wherein said wet chemical etchant is self-limiting so that it stops on the first total intact <111> crystalline plane of said monocrystalline silicon structure.
2. The method of claim 1 wherein said monocrystalline silicon film has a (100) global crystal orientation.
3. The method of claim 2 , wherein after etching to form said monocrystalline silicon structure covered with said hard mask, said sidewalls are aligned with a <110> plane.
4. The method of claim 1 , further comprising: after exposing said monocrystalline silicon structure to said wet chemical etchant, forming a gate dielectric and a gate electrode above said top surface of said monocrystalline silicon structure and on said sidewalls of said monocrystalline silicon structure.
5. The method of claim 4 , further comprising: removing said hard mask prior to forming said gate dielectric and gate electrode.
6. The method of claim 4 , further comprising: forming a source region and drain region in said monocrystalline silicon structure on opposite sides of said gate electrode.
7. The method of claim 1 , wherein said wet chemical etchant has a chemical strength sufficient to etch <100> and <110> planes but insufficient chemical strength to etch <111> planes.
8. The method of claim 1 , wherein the NH 4 OH concentration is between 0.2-1% by volume and said wet chemical etchant has a temperature between 5-25° C.