Methods of forming low interface resistance rare earth metal contacts and structures formed thereby
Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a contact opening in an inter layer dielectric (ILD) disposed on a substrate, wherein a source/drain contact area is exposed, forming a rare earth metal layer on the source/drain contact area, forming a transition metal layer on the rare earth metal layer; and annealing the rare earth metal layer and the transition metal layer to form a metal silicide stack structure.
1. A structure, comprising:
a source/drain region of an NMOS transistor, wherein the source/drain region includes a doped silicon portion;
a tapered recess in an insulating material above the source/drain region, wherein a width of a top portion of the recess is greater than a width of a bottom portion of the tapered recess, and wherein the source/drain region is at a bottom of the tapered recess;
a stacked metal silicide on the source/drain region, wherein the stacked metal silicide is at least partially in the bottom portion of the tapered recess; and
a contact metal on the stacked metal silicide;
wherein the stacked metal silicide comprises a transition metal and a rare earth metal, and at least some of the rare earth metal directly contacts the doped silicon portion of the source/drain region.
2. The structure of claim 1 , wherein the rare earth metal comprises at least one of yttrium, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, and ytterbium.
3. The structure of claim 1 , wherein the transition metal comprises at least one of nickel, titanium and cobalt.
4. The structure of claim 1 , wherein the contact metal is in the tapered recess.
5. The structure of claim 1 , wherein a portion of the rare earth metal layer is segregated towards a silicon/silicide interface of the source/drain region.
6. The structure of claim 1 , wherein the rare earth metal occupies less than 25 percent of a thickness of the stacked metal silicide.
7. The structure of claim 1 , wherein the rare earth metal has a thickness less than 300 angstroms.
8. The structure of claim 1 , wherein the transition metal has a thickness less than 200 angstroms.
9. The structure of claim 1 , wherein the stacked metal silicide does not include oxygen.
10. The structure of claim 1 , wherein the rare earth metal occupies greater than 66% of a thickness of the stacked metal silicide.
11. The structure of claim 1 , wherein the stacked metal silicide includes a region in which the transition metal and the rare earth metal are mixed.
12. The structure of claim 1 , wherein the contact metal includes tungsten or titanium.
13. The structure of claim 1 , wherein the transition metal and the rare earth metal are formed by co-sputtering.
14. The structure of claim 1 , wherein the transition metal and the rare earth metal are interwoven by atomic layer deposition.
15. The structure of claim 1 , further comprising:
a layer of transition metal on the stacked metal silicide.
16. The structure of claim 1 , wherein a thickness of the stacked metal silicide is less than 400 angstroms.
17. The structure of claim 1 , wherein the stacked metal silicide extends below the bottom of the recess.
18. The structure of claim 1 , wherein the insulating material includes an interlayer dielectric.
19. A method of forming a structure in an integrated circuit (IC) device, comprising:
forming a source/drain region of an NMOS transistor, wherein the source/drain region includes a doped silicon portion;
forming an insulating material above the source/drain region;
forming a recess in the insulating material above the source/drain region to expose the source/drain region;
forming a rare earth metal layer in the recess on the source/drain region; and
forming a transition metal layer on the rare earth metal layer in the recess.
20. The method of claim 19 , wherein forming the rare earth metal layer and the forming the transition metal layer are performed without breaking vacuum.
21. The method of claim 19 , wherein a width of a top portion of the recess is greater than a width of a bottom portion of the recess.
22. The method of claim 19 , further comprising:
after forming the transition metal layer, performing an anneal.
23. A structure, comprising:
a source/drain region of an NMOS transistor, wherein the source/drain region includes a doped silicon portion;
a recess in an insulating material above the source/drain region, wherein a width of a top portion of the recess is greater than or equal to a width of a bottom portion of the recess, and wherein the source/drain region is at a bottom of the recess;
a stacked metal silicide on the source/drain region, wherein the stacked metal silicide is at least partially in the bottom portion of the recess; and
a contact metal on the stacked metal silicide;
wherein the stacked metal silicide comprises a transition metal and a rare earth metal, and at least some of the rare earth metal is between the transition metal and the doped silicon portion of the source/drain region.
24. The structure of claim 23 , wherein the stacked metal silicide does not include a layer of oxidized rare earth metal.