IP Library Granted Patent US 7,514,959
Granted Patent B2
US 7,514,959 · App. 11/356,076 · Granted Apr 7, 2009

Structured integrated circuit device

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Quick Facts
Patent No.
US 7,514,959
App. No.
11/356,076
Granted
Apr 7, 2009
Kind
B2
Abstract

A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.

Claims (5)

1. A semiconductor device comprising:

a logic array, said logic array including blocks of logic cells;

metal and via connection layers overlying the blocks of logic cells for providing at least one permanent customized interconnect between various inputs and outputs thereof;

wherein said permanent customized interconnect is customized by a single custom via layer and wherein said permanent customized interconnect includes at least one interconnection to distribute power to at least one of said blocks of logic cells.

2. A semiconductor device as in claim 1 , wherein said at least one interconnection to distribute power to at least one of said blocks of logic cells is customized to connect at least one of said blocks to ground.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2022
From: INTEL CORPORATION
To: TAHOE RESEARCH, LTD.
Reel/Frame 061175/0176 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 11, 2019
From: EASIC CORPORATION
To: INTEL CORPORATION
Reel/Frame 048559/0162 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 17, 2006
From: OR-BACH, ZVI; WURMAN, ZE'EV; LEVINTHAL, ADAM
To: EASIC CORPORATION
Reel/Frame 017576/0207 →