Patent Assignment
Reel/Frame 048559/0162
Assignment of Assignor's Interest
Recorded: 2019-03-11
Pages: 20
Assignor
EASIC CORPORATION
Executed: 2019-03-01
Assignee
INTEL CORPORATION
2200 MISSION COLLEGE BOULEVARD, SANTA CLARA, CALIFORNIA, 95054
Covered Properties
(63)
Structured Integrated Circuit Device
PCT:
PCT/US2005/026227 ↗
Programmable via Modeling
PCT:
PCT/US2007/001484 ↗
Customizable Power and Ground Pins
PCT:
PCT/US2007/062308 ↗
Dynamic Phase Alignment
PCT:
PCT/US2008/059422 ↗
Via-Configurable High-Performance Logic Bloock Architecture
PCT:
PCT/US2011/066457 ↗
Via-Configurable High-Performance Logic Block Involving Transistor Chains
PCT:
PCT/US2013/064364 ↗
Architectural Floorplan for a Structured Asic Manufactured on a 28 Nm Cmos Process Lithographic Node or Smaller
PCT:
PCT/US2013/064371 ↗
Microcontroller or Direct Mode Controlled Network-Fabric on a Structured Asic
PCT:
PCT/US2013/064374 ↗
Clock Network Fishbone Architecture for a Structured Asic Manufactured on a 28 Nm Cmos Process Lithographic Node
PCT:
PCT/US2013/064375 ↗
Temperature Controlled Structured Asic Manufactured on a 28 Cmos Process Lithographic Node
PCT:
PCT/US2013/064379 ↗
Digitally Controlled Delay Line for a Structured Asic Having via Configurable Fabric for High-Speed Interface
PCT:
PCT/US2013/064383 ↗
Structured Integrated Circuit Device with Multiple Configurable via Layers
PCT:
PCT/US2016/023604 ↗
Integrated Circuit Device
Patent:
6,194,912 →
Application:
09/265,998 →
Semiconductor Device
Patent:
6,236,229 →
Application:
09/310,962 →
Semiconductor Device
Patent:
6,331,733 →
Application:
09/371,031 →
Method for Design and Manufacture of Semiconductors
Patent:
6,245,634 →
Application:
09/428,460 →
Scale Uppable Core
Application:
09/455,177 →
Customizable and programmable cell array
Patent:
6,331,790 →
Application:
09/659,783 →
Semiconductor device
Customizable and Programmable Cell Array
Method for Design and Manufacture of Semiconductors
Semiconductor Device
Customizable and Programmable Cell Array
Method for Designing Application Specific Integrated Circuit Structure
Patent:
6,823,499 →
Application:
10/245,140 →
Semiconductor Device Having Borderless Logic Array and Flexible I/O
Customizable and Programmable Cell Array
Method for Fabrication of Semiconductor Device
Structured Integrated Circuit Device
Array of Programmable Cells with Customized Interconnections
Customizable and Programmable Cell Array
Customizable and Programmable Cell Array
Method for fabrication of semiconductor device
Application:
11/097,168 →
Publication:
US 2005/0167701
Structured Integrated Circuit Device
Method for fabrication of semiconductor device
Application:
11/240,380 →
Publication:
US 2006/0033124
Customizable and Programmable Cell Array
Integrated Circuit Communication Techniques
Customizable and Programmable Cell Array
Application:
11/278,452 →
Publication:
US 2006/0176075
Programmable via Modeling
Customizable power and ground pins
Application:
11/354,957 →
Publication:
US 2007/0187808
Structured Integrated Circuit Device
Structured Integrated Circuit Device
Dynamic Phase Alignment
Structured Integrated Circuit Device
Single via Structured Ic Device
Programmable Vias for Structured Asics
Configurable Write Policy in a Memory System
Mems-Based Switching
Programming and Circuit Topologies for Programmable Vias
Application:
12/732,436 →
Publication:
US 2010/0182044
Multiple Write During Simultaneous Memory Access of a Multi-Port Memory Device
Via-Configurable High-Performance Logic Block Architecture
Via-Configurable High-Performance Logic Block Involving Transistor Chains
Architectural Floorplan for a Structured Asic Manufactured on a 28 Nm Cmos Process Lithographic Node or Smaller
Clock Network Fishbone Architecture for a Structured ASIC Manufactured on a 28 NM CMOS Process Lithographic Node
Patent:
8,629,548 →
Application:
13/649,547 →
Microcontroller Controlled or Direct Mode Controlled Network-Fabric on a Structured Asic
Patent:
8,677,306 →
Application:
13/649,551 →
Temperature Controlled Structured ASIC Manufactured on a 28 NM CMOS Process Lithographic Node
Application:
13/649,563 →
Publication:
US 2014/0105246
Digitally Controlled Delay Line for a Structured ASIC Having a Via Configurable Fabric for High-Speed Interface
Application:
13/649,584 →
Publication:
US 2014/0103985
Multiple write during simultaneous memory access of a multi-port memory device
Patent:
46,474 →
Application:
14/579,337 →
Structured Integrated Circuit Device with Multiple Configurable via Layers
Application:
14/676,497 →
Publication:
US 2016/0293541
Multi-Chip Packaged Function Including a Programmable Device and a Fixed Function Die and Use for Application Acceleration
Application:
14/719,430 →
Publication:
US 2016/0124899
Rom Segmented Bitline Circuit
Phase-Change Programmable Vias for Structured ASICs
Application:
60/894,548 →
Via-Configurable High-Performance Logic Block Architecture
Application:
61/426,176 →
Dual Chip Packaged Function Including a Programmable Device and a Fixed Function Easic or Application Specific Integrated Circuit (Asic) Die to Provide Application Acceleration in Conjunction with an External Cpu, Npu or General Purpose Gpu
Application:
62/074,978 →
Related Assignments
(5)
Other recorded transfers of the patents in this record — the chain of ownership.
Merger
May 1, 2014
From: LSI LOGIC CORPORATION
To: LSI CORPORATION
Reel/Frame 032797/0057 →
Patent Security Agreement
May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
Assignment of Assignor's Interest
May 22, 2014
From: LSI CORPORATION
To: EASIC CORPORATION
Reel/Frame 032950/0689 →
Termination and Release of Security Interest in Patent Rights (Releases Rf 032856-0031)
Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
Assignment of Assignor's Interest
Aug 15, 2022
From: INTEL CORPORATION
To: TAHOE RESEARCH, LTD.
Reel/Frame 061175/0176 →