Integrated circuit communication techniques
View Patent ↗An semiconductor device, containing logic blocks and high speed connections between the blocks, where the connections utilize current direction for logic representation rather than voltage level. Such high speed connections comprise differential transmitters which drive a pair of adjacent wires with differential current pulses that are received by a differential receiver which may be put in a low power state between transmissions.
1. A semiconductor device comprising:
a first logic block and a second logic block, and a high speed connection for transferring logic information from said first logic block to said second logic block, wherein said second logic block comprises a register to capture said information; and
a clock distribution system for distributing a clock signal, wherein said clock signal is used to synchronize the powering of said receiver and the timing of said capturing;
wherein said logic information is represented by a direction of current flow in said high speed connection, wherein said second logic block comprises a receiver to convert said direction of current flow to a voltage level logic representation, and wherein said receiver is powered for small periods of time to save circuit power.
2. A semiconductor device according to claim 1 , wherein said clock distribution system distributes the clock using pulses of light.
3. A semiconductor device according to claim 1 , wherein said high speed connection comprises two wires.
4. A semiconductor device according to claim 3 , wherein said two wires are spaced from adjacent signal carriers by a spacing greater than a spacing between said two wires.
5. A semiconductor device according to claim 4 , comprising repeaters to redrive the signals on said two wires.
6. A semiconductor device according to claim 1 , wherein said first logic block comprises a transceiver to convert a voltage level logic representation to said direction of current flow.
7. A semiconductor device according to claim 1 ,
wherein said clock is further used to synchronize said transceiver.
8. The semiconductor device as in claim 1 , wherein said high speed connection further comprises:
a differential driver, and
at least one clocked current sensing receiver;
wherein said differential driver, said two wires, and said current sensing receiver are connected to transmit differential current pulses representing data from said differential driver and to receive said differential current pulses at said receiver when said receiver is clocked.
9. The semiconductor device as in claim 8 , wherein said current sensing receiver comprises:
differential inputs,
a clock input,
a latch, and
a differential receiver;
wherein said differential receiver is disabled by a signal on said clock input, to reduce the power consumed by said current sensing receiver when not receiving data.
10. The semiconductor device as in claim 8 , wherein said differential driver transmits multiple bits of data consisting of said differential current pulses on said two wires prior to said current sensing receiver receiving the first of said current pulses.
11. The semiconductor device as in claim 8 , wherein said two wires are separated from other wires of said semiconductor device by a distance greater than the spacing between said two wires.
12. The semiconductor device as in claim 8 , wherein said two wires are separated from other wires of said semiconductor device by one or more wires connected to ground.
13. A semiconductor device comprising:
a first logic block and a second logic block, and a high speed connection for transferring logic information from said first logic block to said second logic block, wherein said first logic block comprises a transceiver to convert a voltage level logic representation to said direction of current flow; and
a clock distribution system, wherein said clock is used to synchronize said transceiver and the powering of said receiver;
wherein said logic information is represented by a direction of current flow in said high speed connection, wherein said second logic block comprises a receiver to convert said direction of current flow to a voltage level logic representation, and wherein said receiver is powered for small periods of time to save circuit power; and
wherein said clock distribution system distributes the clock using pulses of light.
14. A semiconductor device comprising:
a first logic block and a second logic block, and a high speed connection for transferring logic information from said first logic block to said second logic block, said high speed connection comprising two wires; and
a clock distribution system for distributing a clock signal, wherein said clock signal is used to synchronize the powering of said transmitter;
wherein said logic information is represented by a direction of current flow in said high speed connection, wherein said first logic block comprises a transmitter to convert voltage level logic representations to directions of current flow, and wherein said transmitter is powered for small periods of time to save circuit power; and
wherein said clock distribution system distributes the clock using pulses of light.
15. A semiconductor device comprising:
a first logic block and a second logic block, and a high speed connection for transferring logic information from said first logic block to said second logic block, said high speed connection comprising two wires;
wherein said logic information is represented by a direction of current flow in said high speed connection, wherein said first logic block comprises a transmitter to convert voltage level logic representations to directions of current flow, and wherein said transmitter is powered for small periods of time to save circuit power; and
wherein said transmitter shunts said two wires together when said transmitter is not in a powered state.
16. The semiconductor device as in claim 15 ,
wherein said high speed connection further comprises:
a differential driver, and
at least one clocked current sensing receiver;
wherein said differential driver, said two wires, and said current sensing receiver are connected to transmit differential current pulses representing data from said differential driver and to receive said differential current pulses at said receiver when said receiver is clocked.
17. The semiconductor device as in claim 16 , wherein said current sensing receiver comprises:
differential inputs,
a clock input,
a latch, and
a differential receiver;
wherein said differential receiver is disabled by a signal on said clock input, to reduce the power consumed by said current sensing receiver when not receiving data.
18. The semiconductor device as in claim 17 , wherein said differential driver transmits multiple bits of data consisting of said differential current pulses on said two wires prior to said current sensing receiver receiving the first of said current pulses.
19. The semiconductor device as in claim 17 , wherein said two wires are separated from other wires of said semiconductor device by a distance greater than the spacing between said two wires.
20. The semiconductor device as in claim 17 , wherein said two wires are separated from other wires of said semiconductor device by one or more wires connected to ground.
21. A semiconductor device according to claim 15 , further comprising a clock distribution system for distributing a clock signal, wherein said clock signal is used to synchronize the powering of said transmitter.