Method and apparatus for dynamically adjusting voltage reference to optimize an I/O system
View Patent ↗Described herein is an apparatus for dynamically adjusting a voltage reference level for optimizing an I/O system to achieve a certain performance metric. The apparatus comprises: a voltage reference generator to generate a voltage reference; and a dynamic voltage reference control unit, coupled with the voltage reference generator, to dynamically adjust a level of the voltage reference in response to an event. The apparatus is used to perform the method comprising: generating a voltage reference for an input/output (I/O) system; determining a worst case voltage level of the voltage reference; dynamically adjusting, via a dynamic voltage reference control unit, the voltage reference level based on determining the worst case voltage level; and computing a center of an asymmetrical eye based on the dynamically adjusted voltage reference level.
1. A computing system, comprising:
a processor; and
a dynamic random access memory (DRAM) coupled to the processor, the DRAM to determine logic state of received digital data based on a dynamically adjustable reference voltage, wherein a controller is operable to set, via software, the dynamically adjustable reference voltage to one of a plurality of different reference voltage options, wherein the controller is a hardware,
wherein the controller is to dynamically adjust the dynamically adjustable reference voltage in view of a timing budget to control a buffer power level.
2. The computing system of claim 1 , wherein the controller is capable of dynamically setting the dynamically adjustable reference voltage to one of a plurality of different voltage levels.
3. The computing system of claim 1 , wherein the controller is to dynamically set the dynamically adjustable reference voltage to different reference voltages for identifying operational limits.
4. The computing system of claim 1 , wherein the software is to execute on the processor.
5. The computing system of claim 1 , wherein the controller is to sweep through the different reference voltage options in accordance with one or more test patterns to identify a desired reference voltage.
6. The computing system of claim 5 , wherein the desired reference voltage is to provide desired power dissipation for a desired memory data rate timing objective.
7. The computing system of claim 1 , wherein the controller is to train a voltage reference level in conjunction with a memory initialization.
8. The computing system of claim 7 , wherein the memory initialization is part of a system boot procedure.
9. An apparatus, comprising:
a dynamic random access memory (DRAM) module with at least one selectably adjustable reference voltage generator using a digital-to-analog converter (DAC), wherein the at least one selectably adjustable reference voltage generator includes the DAC to generate a selected voltage reference level from an input command word, and wherein the at least one selectably adjustable reference voltage generator is to dynamically adjust the dynamically adjustable reference voltage in view of a timing budget to control a buffer power level.
10. The apparatus of claim 9 , wherein the DRAM module is a DDR4 compliant memory module.
11. The apparatus of claim 9 , wherein the at least one selectably adjustable reference voltage generator includes a resistor ladder structure to generate a plurality of different selectable reference voltage options.
12. Machine readable media having instructions stored thereon, that when executed, cause one or more machines to perform an operation, the operation comprising:
testing two or more different reference voltage levels for a dynamic random access memory (DRAM);
evaluating one or more parameters associated with the DRAM for the tested two or more different reference voltage levels; and
selecting one of the tested two or more different reference voltage levels based on the evaluated one or more parameters, wherein the two or more different reference voltage levels are generated by a circuit inside the DRAM.
13. The machine readable media of claim 12 , wherein the instructions are part of a system initialization routine.