Conductive paths through dielectric with a high aspect ratio for semiconductor devices
View Patent ↗Conductive paths through a dielectric are described that have a high aspect ratio for semiconductor devices. In one example, a plurality of conductive connection pads are formed on a semiconductor substrate to connect to circuitry formed on the substrate. A post is formed on each of a subset of the connection pads, the posts being formed of a conductive material. A dielectric layer is formed over the semiconductor substrate including over the connection pads and the posts. Holes are formed by removing the dielectric layer directly over the posts. The formed holes are filled with a conductive material and a connector is formed over each filled hole.
1. A method comprising:
forming a plurality of conductive connection pads on a semiconductor substrate to connect to circuitry formed on the substrate;
forming a post on at least one of the connection pads, the post being formed of a. conductive material;
forming a dielectric layer over the semiconductor substrate including over the connection pads and the post;
forming a hole by removing the dielectric layer directly over the post to expose the post with dielectric remaining between at least some the conductive pads;
filling the formed hole with a conductive material to electrically contact the post; and
forming a connector over the filled hole with dielectric remaining between at least some of the conductive connection pads.
2. The method of claim 1 , wherein the post extends from the substrate to a height of about one half of the dielectric layer.
3. The method of claim 1 , wherein the post and the formed hole have a cross-sectional surface area and the post has a larger cross-sectional surface area than the hole.
4. The method of claim 1 , wherein the conductive material of the post and the conductive material of filling the hole is the same conductive material.
5. The method of claim 1 , wherein the conductive material is copper.
6. The method of claim 1 , wherein forming a plurality of conductive connection pads comprises forming a first subset of the connection pads having a first diameter and a second subset of the connection pads having a second larger diameter and wherein forming a post comprises forming a post only on the pads of the first subset of connection pads.
7. The method of claim 6 , wherein forming holes comprise forming holes using a patterned photoresist and etching the dielectric layer over the conductive connection pads.
8. The method of claim 6 , wherein forming holes comprises using. photostructurable dielectric, exposing a portion of the dielectric over the conductive connection pads and removing the unexposed dielectric.
9. The method of claim 1 , wherein forming a plurality of conductive connection pads comprises funning a first subset of the connection pads having a first diameter and a second subset of the connection pads having a second larger diameter and wherein forming a post comprises forming a post on the pads of the first subset and the second subset of connection pads and wherein forming holes comprises forming holes by laser ablation.
10. The method of claim 1 , further comprising:
dicing the semiconductor substrate after forming the post to form a plurality of dies; and
embedding at least a portion of the plurality of dies in a mold compound with the post exposed, and
wherein forming a dielectric: layer is performed after embedding.
11. The method of claim 10 , wherein embedding further comprises:
placing the at least a portion of the dies on a tape so that the post is embedded in the tape, the tape being attached to a temporary carrier;
applying the mold compound over the dies and the temporary carrier; and
removing the tape and the temporary carrier to expose the post.
12. The method of claim 1 , further comprising forming a redistribution layer over the dielectric layer while filling the hole and wherein forming a connector comprises forming a solder ball array.
13. The method of claim 1 , wherein forming a hole comprises reducing the height of the dielectric to expose the post over the post and also over the entire substrate.
14. The method of claim 1 , wherein forming a post comprises:
applying a protective layer over each of a subset of the connection pads;
applying a seed layer over the semiconductor substrate;
patterning a photoresist over the semiconductor substrate with openings over the subset of connection pads;
electroplating the openings with a conductive material to form the posts; and removing the patterned photoresist.
15. The method of claim 1 , wherein forming a hole comprises reducing the height of the dielectric to expose the post over the post and also over the entire substrate.
16. The method of claim 15 , wherein reducing comprises applying a process selected from the set of grinding, polishing, cutting, and etching.
17. The method of claim 1 , wherein forming a hole comprises sputtering a seed layer over the dielectric, depositing and patterning a photoresist over the seed layer, and wherein filing the hole comprises electroplating over the opening in the patterned photoresist, stripping the photoresist and etching the seed layer.