Low resistance interconnect

1. An apparatus comprising:

a transistor formed on a substrate; and

a metal interconnect formed in a dielectric layer above the transistor, wherein:

the interconnect comprises a copper layer and a barrier layer that separates the copper layer from the dielectric layer, and

the barrier layer comprises tantalum and niobium.

2. The apparatus of claim 1 , wherein both the tantalum and the niobium have a body centered cubic (BCC) crystal structure.

3. The apparatus of claim 1 , wherein the substrate includes silicon.

4. The apparatus of claim 1 , wherein the barrier layer is: (a) on a sidewall of the interconnect at a horizontal thickness, and (c) along a bottom of the interconnect at a vertical thickness that is greater than the horizontal thickness.

5. The apparatus of claim 1 , wherein the barrier layer is a physical vapor deposition (PVD) layer sputtered within the interconnect.

6. The apparatus of claim 1 , wherein the barrier layer is not a conformal thin film that conforms in equal thicknesses along first and second sidewalls and a bottom of the interconnect.

7. The apparatus of claim 1 , wherein the tantalum and the niobium are completely miscible with each other.

8. The apparatus of claim 1 , wherein the barrier layer includes at least 5% niobium.

9. The apparatus of claim 1 , wherein:

a first horizontal axis, parallel to the substrate, intersects the barrier layer along a bottom of the interconnect but does not intersect the copper;

a second horizontal axis intersects the barrier layer, on first and second sidewalls of the interconnect, and the copper but does not intersect the barrier layer along the bottom of the interconnect;

the barrier layer, along the bottom of the interconnect, has a vertical thickness that intersects the first horizontal axis;

the barrier layer along at least one of the first or second sidewalls has a horizontal thickness that intersects the second horizontal axis; and

the vertical thickness is greater than the horizontal thickness.

10. The apparatus of claim 1 , wherein the barrier layer has a volume resistivity less than 35 micro-Ohm-cm.

11. The apparatus of claim 1 including a system on a chip with embedded memory including a memory array comprising the interconnect.

12. The apparatus of claim 1 , wherein:

the interconnect includes a trench formed directly over a via;

first and second sidewalls of the interconnect are included completely within the via;

a bottom of the interconnect is included within the via.

13. The apparatus of claim 1 , wherein the barrier layer directly contacts the dielectric layer.

14. An apparatus comprising:

a via layer, including a dielectric, between a substrate and a metal layer; and

an interconnect included in the via layer and coupled to the metal layer;

wherein:

the interconnect includes copper and a barrier layer that separates the copper from the dielectric;

the barrier layer is (a) on a first sidewall of the interconnect at a horizontal thickness, and (b) along a bottom of the interconnect at a vertical thickness that is greater than the horizontal thickness; and

the barrier layer includes an alloy including Tantalum and an element that includes at least one of Niobium, Tungsten, or Molybdenum.

15. The apparatus of claim 14 , wherein both the tantalum and the element have a body centered cubic (BCC) crystal structure.

16. The apparatus of claim 15 , wherein the barrier layer is sputtered within the interconnect.

17. The apparatus of claim 15 , wherein the alloy includes at least 5% niobium.

18. The apparatus of claim 15 , wherein:

the interconnect includes a trench formed directly over a via;

the first sidewall is included completely within the via;

the bottom of the interconnect is included within the via.