Hybrid phase field effect transistor
An insulating layer is deposited over a transistor structure. The transistor structure comprises a gate electrode over a device layer on a substrate. The transistor structure comprises a first contact region and a second contact region on the device layer at opposite sides of the gate electrode. A trench is formed in the first insulating layer over the first contact region. A metal-insulator phase transition material layer with a S-shaped IV characteristic is deposited in the trench or in the via of the metallization layer above on the source side.
1. An apparatus, comprising:
a fin comprising opposing sidewalls and a top surface between the opposing sidewalls on a substrate;
a gate electrode on a channel portion of the fin, the fin having a first source/drain portion and a second source/drain portion; and
a first metal-insulator phase transition material layer on the first source/drain portion, wherein the metal-insulator phase transition material layer is disposed on the top surface and the opposing sidewalls of the fin.
2. The apparatus of claim 1 , further comprising
a second metal-insulator phase transition material layer on the second source/drain portion.
3. The apparatus of claim 1 , further comprising
a first capping layer underneath the first metal-insulator phase transition material layer.
4. The apparatus of claim 1 , further comprising
a second capping layer on the first metal-insulator phase transition material layer.
5. The apparatus of claim 1 , further comprising
a metallization layer above the first source/drain portion.
6. The apparatus of claim 1 , further comprising
an insulating layer having a trench on the first source/drain region, wherein the first metal-insulator phase transition material layer is deposited within the trench.
7. The apparatus of claim 1 , wherein the metal-insulator phase transition material layer includes a transition metal oxide, an ABO 3 material, or any combination thereof.
8. A system on a chip comprising:
a plurality of transistors; at least one of the transistors comprising
a fin comprising a channel region; and a drain region coupled to the channel region;
a common source region coupled to the plurality of transistors; and
a metal-insulator phase transition material layer within the common source region.
9. The system of claim 8 , wherein an area size of the metal-insulator phase transition material layer is not less than the area size of the common source region.
10. The system of claim 9 , wherein as the area size of the metal-insulator phase transition material layer increases, a voltage at which at least one of the transistors turns ON decreases.
11. The system of claim 9 , wherein as the area size of the metal-insulator phase transition material layer decreases, a leakage current of at least one of the transistors decreases.
12. The system of claim 8 , wherein the metal-insulator phase transition material layer is embedded into the common source region.
13. The system of claim 8 , further comprising
an insulating layer comprising a trench on the common source region, wherein the metal-insulator phase transition material layer is deposited within the trench.
14. The system of claim 8 , further comprising
a metallization layer over the common source region, wherein the metal-insulator phase transition material layer is embedded within the metallization layer.
15. An electronic device system comprising:
a plurality of transistor structures on a substrate; at least one of the transistor structures comprising a fin comprising a source/drain region coupled to a channel region;
a first insulating layer over the plurality of transistor structures;
a metallization layer on the first insulating layer; and
a stack comprising a metal-insulator phase transition material layer on the portion of the metallization layer, wherein the metal-insulator phase transition material layer is in a trench in a second insulating layer that exposes the portion of the metallization layer.
16. The electronic device system of claim 15 , wherein the stack comprises
a conductive layer on the metal-insulator phase transition material layer.
17. The electronic device system of claim 15 , wherein the stack comprises
a capping layer adjacent to the metal-insulator phase transition material layer.
18. A computing system comprising:
a chip including
an electronic device comprising
a fin comprising opposing sidewalls and a top surface between opposing sidewalls on a substrate;
a gate electrode on a channel portion of the fin, the fin having a first source/drain portion and a second source/drain portion; and
a first metal-insulator phase transition material layer on the first source/drain portion, wherein the metal-insulator phase transition material layer is disposed on the top surface and the opposing sidewalls of the fin.
19. The computing system of claim 18 , further comprising
a second metal-insulator phase transition material layer on the second source/drain portion.
20. The computing system of claim 18 , further comprising
a first capping layer underneath the first metal-insulator phase transition material layer.
21. The computing system of claim 18 , further comprising
a second capping layer on the first metal-insulator phase transition material layer.
22. The computing system of claim 18 , further comprising
a metallization layer above the first source/drain portion.
23. The computing system of claim 18 , further comprising
an insulating layer having a trench on the first source/drain region, wherein the first metal-insulator phase transition material layer is deposited within the trench.
24. The computing system of claim 18 , wherein the metal-insulator phase transition material layer includes a transition metal oxide, an ABO 3 material, or any combination thereof.