Hybrid phase field effect transistor
View Patent ↗An insulating layer is deposited over a transistor structure. The transistor structure comprises a gate electrode over a device layer on a substrate. The transistor structure comprises a first contact region and a second contact region on the device layer at opposite sides of the gate electrode. A trench is formed in the first insulating layer over the first contact region. A metal-insulator phase transition material layer with a S-shaped IV characteristic is deposited in the trench or in the via of the metallization layer above on the source side.
1. An electronic device, comprising:
a gate electrode on a substrate,
a pair of source/drain regions on the substrate at opposite sides of the gate electrode;
a pair of contact layers coupled to the pair of source/drain regions;
a metallization layer that is a part of a back end metallization of the electronic device over the pair of contact layers;
a trench in an insulating layer to expose a portion of the metallization layer; and
a metal-insulator phase transition material layer on the portion of the metallization layer within the trench.
2. The electronic device of claim 1 , wherein the metal-insulator phase transition material layer is formed to couple to only one of the two contact layers.
3. The electronic device of claim 1 , wherein the metal-insulator phase transition material layer is on a first capping layer within the trench.
4. The electronic device of claim 3 , wherein the first capping layer is formed on the portion of the metallization layer.
5. The electronic device of claim 1 , wherein the metal-insulator phase transition material layer is coupled to the source region.
6. The electronic device of claim 1 , wherein the metal-insulator phase transition material layer is coupled to the drain region.
7. The electronic device of claim 1 , wherein the insulating layer is formed around the gate electrode, the contact layers, and the metal-insulator phase transition material layer.
8. The electronic device of claim 3 , wherein the metal-insulator phase transition material layer is coupled to the source/drain region.
9. The electronic device of claim 1 , wherein the metal-insulator phase transition material layer is sandwiched between the first capping layer and a second capping layer.
10. The electronic device of claim 1 , wherein the thickness of the metal-insulator phase transition material layer is from 2 nanometers to 100 nm.
11. The electronic device of claim 1 , wherein the metal-insulator phase transition material layer includes a transition metal oxide, an ABO 3 material, or any combination thereof.
12. The electronic device of claim 1 , wherein the substrate comprises a semiconductor fin.
13. The electronic device of claim 1 , wherein the metallization layer comprises a plurality of metallization layers.