Germanium-based quantum well devices
A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.
1. A method of forming a microelectronic device, comprising:
forming a germanium quantum well channel region transistor, comprising:
forming a lower barrier region;
forming a germanium channel region on the lower barrier region;
forming an upper barrier region on the germanium channel region;
forming a gate dielectric abutting the upper barrier region;
forming a gate electrode on the gate dielectric;
forming a source abutting the upper barrier region; and
forming a drain abutting the upper barrier region;
wherein the gate dielectric abuts the source and the drain;
forming a group III-V material quantum well channel region transistor, comprising:
forming a lower barrier region;
forming a group III-V material channel region on the lower barrier region;
forming an upper barrier region on the germanium channel region;
forming a gate dielectric abutting the upper barrier region;
forming a gate electrode on the gate dielectric;
forming a source abutting the upper barrier region; and
forming a drain abutting the upper barrier region;
wherein the gate dielectric abuts the source and the drain; and
forming an isolation region disposed between the germanium quantum well region transistor and the group III-V material quantum well channel region transistor;
wherein the germanium quantum well channel region transistor, the group III-V material quantum well channel region transistor, and the isolation region are formed on a common substrate and wherein the isolation region contacts the common substrate.
2. The method of claim 1 , wherein forming the isolation region comprises forming the isolation region to abut the germanium quantum well channel region transistor and the group III-V material quantum well channel region transistor.
3. The method of claim 1 , wherein forming the lower barrier region of the germanium quantum well channel region transistor comprises forming a group III-V material lower barrier region.
4. The method of claim 1 , wherein forming the lower barrier region of the germanium quantum well channel region transistor comprises forming a GaAs lower barrier region.
5. The method of claim 1 , wherein forming the lower barrier region of the germanium quantum well channel region transistor comprises forming a silicon germanium barrier region.
6. The method of claim 5 , wherein forming the silicon germanium lower barrier region of the germanium quantum well channel region transistor comprises forming the silicon germanium lower barrier region having a higher percentage of silicon in a portion of the lower barrier region further from the quantum well channel region and a lower percentage of silicon in a portion of the lower barrier region closer to the quantum well channel region.
7. The method of claim 1 , wherein forming the lower barrier region of the germanium quantum well channel region transistor comprises forming a silicon germanium lower barrier region and forming the upper barrier region of the germanium quantum well channel region transistor comprises forming a group III-V material upper barrier region.
8. The method of claim 1 , wherein forming the lower barrier region of the group III-V material quantum well channel region transistor comprises forming an InAlAs lower barrier region.
9. The method of claim 1 , wherein forming the channel region of the group III-V material quantum well channel region transistor comprises forming an InGaAs channel region.