Instruction for accelerating SNOW 3G wireless security algorithm

1. An apparatus comprising:

a plurality of vector registers including a first vector register and a second vector register; and

execution circuitry coupled to the plurality of vector registers, the execution circuitry operative to:

receive a first instruction to perform wireless security operations;

receive a first operand of the first instruction specifying the first vector register that stores a current state of a finite state machine (FSM);

receive a second operand of the first instruction specifying the second vector register that stores data elements of a liner feedback shift register (LFSR) that are needed for updating the FSM; and

execute the first instruction to produce a updated state of the FSM and an output of the FSM in a destination operand of the first instruction.

2. The apparatus of claim 1 , wherein the plurality of vector registers include a third vector register, the execution circuitry operative to:

receive a second instruction to perform an update to the LFSR;

receive a first operand of the second instruction specifying the second vector register;

receive a second operand of the second instruction specifying the third vector register that stores half of the data elements in the LFSR that are not in the second vector register; and

execute the second instruction to produce an updated left-most data element of the LFSR and a first set of shifted data elements of the LFSR in a destination operand of the second instruction.

3. The apparatus of claim 2 , wherein the execution circuitry is operative to:

receive a third instruction to perform the update to the LFSR;

receive a first operand of the third instruction specifying the second vector register;

receive a second operand of the third instruction specifying the third vector register; and

execute the third instruction to produce a second set of shifted data elements of the LFSR in a destination operand of the third instruction.

4. The apparatus of claim 3 , wherein the execution circuitry is operative to:

execute the first instruction, the second instruction and the third instruction in a first update phase that uses a first set of source operands;

execute the first instruction, the second instruction and the third instruction in a second update phase that uses a second set of source operands; and

repeat the first update phase and the second update phase in a loop to update the FSM and the LFSR.

5. The apparatus of claim 1 , wherein the first instruction is a Single Instruction Multiple Data (SIMD) instruction that updates three FSM state registers and generates the output of the FSM in parallel.

6. The apparatus of claim 1 , wherein the execution circuitry is operative to update the three FSM state registers by performing eight table look-ups in parallel.

7. The apparatus of claim 1 , wherein the execution circuitry is operative to execute the first instruction in a SIMD pipeline.

8. A method comprising:

receiving by execution circuitry a first instruction to perform wireless security operations;

receiving a first operand of the first instruction specifying a first vector register that stores a current state of a finite state machine (FSM);

receiving a second operand of the first instruction specifying a second vector register that stores data elements of a liner feedback shift register (LFSR) that are needed for updating the FSM; and

executing the first instruction to produce a updated state of the FSM and an output of the FSM in a destination operand of the first instruction.

9. The method of claim 8 , further comprising:

receiving a second instruction to perform an update to the LFSR;

receiving a first operand of the second instruction specifying the second vector register;

receiving a second operand of the second instruction specifying a third vector register that stores half of the data elements in the LFSR that are not in the second vector register; and

executing the second instruction to produce an updated left-most data element of the LFSR and a first set of shifted data elements of the LFSR in a destination operand of the second instruction.

10. The method of claim 9 , further comprising:

receiving a third instruction to perform the update to the LFSR;

receiving a first operand of the third instruction specifying the second vector register;

receiving a second operand of the third instruction specifying the third vector register; and

executing the third instruction to produce a second set of shifted data elements of the LFSR in a destination operand of the third instruction.

11. The method of claim 10 , further comprising:

executing the first instruction, the second instruction and the third instruction in a first update phase that uses a first set of source operands;

executing the first instruction, the second instruction and the third instruction in a second update phase that uses a second set of source operands; and

repeating the first update phase and the second update phase in a loop to update the FSM and the LFSR.

12. The method of claim 8 , wherein the first instruction is a Single Instruction Multiple Data (SIMD) instruction that updates three FSM state registers and generates the output of the FSM in parallel.

13. The method of claim 12 , further comprising:

updating the three FSM state registers by performing eight table look-ups in parallel.

14. The method of claim 8 , further comprising:

executing the first instruction in a SIMD pipeline.

15. The method of claim 8 , wherein the SNOW 3 G wireless security operations are executed in one of two modes that include an initialization mode and a key-stream mode.

16. A system comprising:

memory; and

a processor coupled to the memory, the processor comprising:

a plurality of vector registers including a first vector register and a second vector register; and

execution circuitry coupled to the plurality of vector registers, the execution circuitry operative to:

receive a first instruction to perform wireless security operations;

receive a first operand of the first instruction specifying the first vector register that stores a current state of a finite state machine (FSM);

receive a second operand of the first instruction specifying the second vector register that stores data elements of a liner feedback shift register (LFSR) that are needed for updating the FSM; and

execute the first instruction to produce a updated state of the FSM and an output of the FSM in a destination operand of the first instruction.

17. The system of claim 16 , wherein the plurality of vector registers include a third vector register, the execution circuitry operative to:

receive a second instruction to perform an update to the LFSR;

receive a first operand of the second instruction specifying the second vector register;

receive a second operand of the second instruction specifying the third vector register that stores half of the data elements in the LFSR that are not in the second vector register; and

execute the second instruction to produce an updated left-most data element of the LFSR and a first set of shifted data elements of the LFSR in a destination operand of the second instruction.

18. The system of claim 17 , wherein the execution circuitry is operative to:

receive a third instruction to perform the update to the LFSR;

receive a first operand of the third instruction specifying the second vector register;

receive a second operand of the third instruction specifying the third vector register; and

execute the third instruction to produce a second set of shifted data elements of the LFSR in a destination operand of the third instruction.

19. The system of claim 18 , wherein the execution circuitry is operative to:

execute the first instruction, the second instruction and the third instruction in a first update phase that uses a first set of source operands;

execute the first instruction, the second instruction and the third instruction in a second update phase that uses a second set of source operands; and

repeat the first update phase and the second update phase in a loop to update the FSM and the LFSR.

20. The system of claim 16 , wherein the first instruction is a Single Instruction Multiple Data (SIMD) instruction that updates three FSM state registers and generates the output of the FSM in parallel.

21. The system of claim 20 , wherein the execution circuitry is operative to update the three FSM state registers by performing eight table look-ups in parallel.