Disabling outbound drivers for a last memory buffer on a memory channel
View Patent ↗Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface.
1. A first memory buffer device, comprising:
an outbound receiving logic to receive a first data from a first uni-directional link, the first uni-directional link to electrically couple the first memory buffer device with at least a host controller;
an outbound redriving logic to drive the first data across a second uni-directional link, the second uni-directional link to electrically couple the first memory buffer device with at least a second memory buffer device, the outbound redriving logic further to disable driving the first data across the second uni-directional link if the second memory buffer device is not coupled with the second uni-directional link;
an inbound receiving logic to receive a second data from a third uni-directional link, the third uni-directional link to electrically couple the first memory buffer device with the at least second memory buffer device; and
an inbound redriving logic to drive the second data across a fourth uni-directional link, the fourth uni-directional link to electrically couple the first memory buffer device with the at least host controller.
2. The first memory buffer device of claim 1 , wherein the first memory buffer device is attached to a printed circuit board (PCB).
3. The first memory buffer device of claim 2 , wherein at least one dynamic random access memory (DRAM) device is attached to the PCB.
4. The first memory buffer device of claim 3 , wherein the first memory buffer device is coupled to the at least one DRAM device through a memory input/output (I/O) interface.